Image processing is essential in a wide range of applications, like medical imaging and remote sensing, where precise visual scene interpretation is critical. However, noise is typically introduced during the process of creating, editing, transmitting, and storing color images, diminishing their visual quality and the efficacy of later image processing operations. Digital image processing relies heavily on noise reduction, also known as denoising, which seeks to get rid of unwanted noise without altering the quality of the image's essential details. In this research, we show how to use a hardware/software codesign strategy to efficiently construct the Adaptive Vector Directional Distance Filter (AVDDF) on a Field-Programmable Gate Array (FPGA). To streamline the development process, we use a high-level synthesis (HLS) pipeline with the Xilinx Vivado HLS tool. The software module is written in C/C++ and runs on a high-performance Reduced Instruction Set Computer (RISC). Comparisons are done with well-established denoising techniques like the Vector Directional Distance Filter (VDDF) and the Vector Directional Filter (VDF) to evaluate the effectiveness of the AVDDF technique. For performance comparisons, evaluation criteria such as the Structural Similarity Index (SSIM), Peak Signal-to-Noise Ratio (PSNR), and Mean Squared Error (MSE) are used. In addition, the performance of the FPGA is measured in terms of its Look-Up Tables (LUTs), Flip-Flops (FFs), BRAM_18K (Block RAMs), and DSP48E (Digital Signal Processing Blocks) using Verilog. The area, power, and delay performance of the suggested ASIC implementation is evaluated as well. The findings of this study prove that the AVDDF denoising method is effective in enhancing image quality while keeping crucial image properties unchanged.