Low Cost Ternary Content Addressable Memory Based on Early Termination Precharge Scheme

Lee, Kyeongho; Ko, Geon

doi:10.1109/iscas.2019.8702372

Cited by 7 publications

(4 citation statements)

References 7 publications

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“…MLDC [15] and SCSL [23] CAMs offer moderate energy as well as delay. Adaptive [20] and ETP [21] designs lower the energy for per search (EfS N ) but the delay (Delay N ) is considerable. Proposed CAM reduces the delay by approximately 22%, 26%, and 29%, compared to the cascaded‐CAM [25], adaptive‐CAM, and ETP‐CAM, respectively.…”

Section: Results and Performance Analysismentioning

confidence: 99%

“…For a legitimate comparison of the performance with the proposed design implementation, energy and delay of the referred designs are normalized using Equations ( 5) and ( 6) as presented in [4]. Reference 2016 [1] 2018 [9] 2018 [15] 2018 [20] 2019 [21] 2020 [22] 2019 [23] 2016 [25] 2017 [26]…”

Section: Performance Comparison Summarymentioning

confidence: 99%

“…Gated ML pull-down technique limits ML discharging to reduce power while ML boosting scheme decreases ML delay [20]. Based on mismatch's pre-decision, early termination of precharge (ETP) reduces ML swing to save power [21]. Charge-refill technique in two-layer ML sensing (TLMLS) design reduces the second layer's precharge and discharge levels to lessen precharge power between consecutive searches [22].…”

Section: Introductionmentioning

confidence: 99%

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Match‐line control unit for power and delay reduction in hybrid CAM

Hussain

Mahendra²,

Mishra

et al. 2021

IET Circuits, Devices & Syst

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Content addressable memory (CAM) is a hardware search engine utilised for accelerating translation and table look‐up in network routers and data processing systems. This article proposes a NAND‐NOR match‐line (ML) based CAM architecture with the main goals of elevating search performance and energy efficiency. A competent ML control unit (MLCU) is introduced to provide a short discharge path for output match‐line after processing the ML sections. In this architecture, tag mismatch based on memory traces is utilised (in NAND‐MLs) to deactivate redundant NOR‐MLs in an attempt to reduce the overall ML switching activity. Based on the decision of NAND‐ML partition, the MLCU restores the charge to reduce ML glitches during the evaluation phase. Match‐line delay of the proposed 64×32‐bit hybrid CAM is 366.90 ps in a standard 45‐nm technology at 1 V, which is 56.51% and 72.55% reductions compared to a conventional CAM and a segmented CAM, respectively. Reduction in precharge power and search power of the presented CAM leads to 6× enhancements of power‐delay‐product from existing hybrid CAMs. The proposed CAM can operate up to low supply voltages by dissipating only 0.10 fJ/bit/search at 0.5 V.

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Section: Results and Performance Analysismentioning

confidence: 99%

Section: Performance Comparison Summarymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Match‐line control unit for power and delay reduction in hybrid CAM

Hussain

Mahendra²,

Mishra

et al. 2021

IET Circuits, Devices & Syst

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“…A TCAM [7] [8] has three modes of operation, namely : Read, Write and Compare. Since TCAM has a compare operation feature, it performs this feature in two parts : storage and a comparison .…”

Section: Proposed Methodologymentioning

confidence: 99%

Multi-Core Eight Bit Ternary Content-Addressable Memory Design Based Image Learning System

Kumar*

2019

IJITEE

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In this research work, the image is learned to find features to make use of during its analysis and a genetic apices based low power Ternary Content-Addressable Memory (TCAM) is designed to implement the proposed image learning system. A technique called Content Matching Search Register is proposed in this work to perform the image learning operations in proposed TCAM architecture. This paper proposes an ImOFF algorithm for image analysis. The focus of this multi-core TCAM (MC-TCAM) is to make fast computations and search based designs. The focus application of this research work is in the design of low power On-board Embedded-VLSI chip to perform image analysis. Proposed multi-core eight bit Ternary TCAM (MCEB-TCAM) is analyzed using IC design tools in 90nm technology, using Verilog hardware description language and usage of Cadence for layout generation and parasitic extraction of the circuit components.

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A Novel Transition Metal Dichalcogenide based Spin Transfer Torque Ternary Content Addressable Memory Design for Match Line Sense Amplifier

Yatheesh¹,

Prasad²

2020

2020 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)

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Low Cost Ternary Content Addressable Memory Based on Early Termination Precharge Scheme

Cited by 7 publications

References 7 publications

Match‐line control unit for power and delay reduction in hybrid CAM

Match‐line control unit for power and delay reduction in hybrid CAM

Multi-Core Eight Bit Ternary Content-Addressable Memory Design Based Image Learning System

A Novel Transition Metal Dichalcogenide based Spin Transfer Torque Ternary Content Addressable Memory Design for Match Line Sense Amplifier

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