Low Cost SoC Design of H.264/AVC Decoder for Handheld Video Player

Wisayataksin, Sumek; Li, Dongju; Isshiki, Takaaki; Kunieda, Hiroaki

doi:10.1093/ietfec/e91-a.4.1197

Cited by 2 publications

(3 citation statements)

References 8 publications

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“…However, ASIC can only support a single video standard due to the lack of ASIC flexibility. Platform-based SoC [22], which consists of a RISC and an ASIC decoder core, targets mobile applications such as a handheld video player. The important design considerations are the size, power consumption and cost, not performance and flexibility.…”

Section: Implementing Resultsmentioning

confidence: 99%

“…For a mobile appliance, the resource cost of the system becomes a more important factor. Compared with MB level pipelining architecture in conventional designs, the 4 × 4-block level parallelism [21], [22] improve the utilization of processing units, decrease operation complexity, optimize circuit size and eliminates the bubbles that exist in MB-level pipeline. But the increased external memory access in MC is a penalty.…”

Section: Problem Of Choosing Data Sizementioning

confidence: 99%

“…For H.264, MC adopts a variable block size, and the 4 × 4 sub-MB is the minimum partition block. Previous researchers [22], [28] have used a 4 × 4 block-based MC to support different block sizes. However, this scheme forces each 4 × 4 block to always load 9 × 9 pixels, as shown in Fig.…”

Section: Mapping Strategy Of MC Onto Remus-iimentioning

confidence: 99%

See 2 more Smart Citations

Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC

Gu-gang

Cao

Yang

et al. 2013

IEICE Trans. Inf. & Syst.

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SUMMARYOne of the largest challenges for coarse-grained reconfigurable arrays (CGRAs) is how to efficiently map applications. The key issues for mapping are (1) how to reduce the memory bandwidth, (2) how to exploit parallelism in algorithms and (3) how to achieve load balancing and take full advantage of the hardware potential. In this paper, we propose a novel parallelism scheme, called 'Hybrid partitioning', for mapping a H.264 high definition (HD) decoder onto REMUS-II, a CGRA systemon-chip (SoC). Combining good features of data partitioning and task partitioning, our methodology mainly consists of three levels from top to bottom: (1) hybrid task pipeline based on slice and macroblock (MB) level; (2) MB row-level data parallelism; (3) sub-MB level parallelism method. Further, on the sub-MB level, we propose a few mapping strategies such as hybrid variable block size motion compensation (Hybrid VBSMC) for MC, 2D-wave for intra 4 × 4, parallel processing order for deblocking. With our mapping strategies, we improved the algorithm's performance on REMUS-II. For example, with a luma 16 × 16 MB, the Hybrid VBSMC achieves 4 times greater performance than VBSMC and 2.2 times greater performance than fixed 4 × 4 partition approach. Finally, we achieve 1080p@33fps H.264 high-profile (HiP)@level 4.1 decoding when the working frequency of REMUS-II is 200 MHz. Compared with typical hardware platforms, we can achieve better performance, area, and flexibility. For example, our performance achieves approximately 175% improvement than that of a commercial CGRA processor XPP-III while only using 70% of its area.

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Section: Implementing Resultsmentioning

confidence: 99%

Section: Problem Of Choosing Data Sizementioning

confidence: 99%