Low-cost reconfigurable VLSI architecture for fast fourier transform

Xiao, H.; Pan, An; Chen, Yun; Zeng, Xiaoyang

doi:10.1109/tce.2008.4711210

Cited by 17 publications

(7 citation statements)

References 10 publications

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“…Also, this work is verified via MATLAB and C simulation. Table II and Table III illustrated comparison of this work with several long-length FFT designs in [5]- [7]. We figure out that the optimal bit number for data representation is 11bits and twiddle factor is 10bits in our work.…”

Section: Performance Evaluation and Comparisonmentioning

confidence: 86%

Low-cost variable-length FFT processor for DVB-T/H applications

Jung

Lee

2010

2010 IEEE Asia Pacific Conference on Circuits and Systems

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This paper presents a low-cost variable-length FFT processor for digital video broadcasting -terrestrial / handheld (DVB-T/H) systems employing pipelined shared-memory architecture, in which a radix-2/2 3 /2 4 FFT algorithm, multi-path delay commutator (MDC), a novel data scaling approach are exploited. Based on this architecture, novel low cost index block scaling approach was proposed to increase area efficiency. Also, an elaborate memory configuration scheme applied to make single-port SRAM without degrading throughput rate. The SQNR performance of this FFT processor has signal-toquantization noise ratio (SQNR) of 8K-point FFT is about 46.8 dB at 11bit internal word length for QPSK/16QAM modulation. The maximum clock frequency of proposed design is 110 MHz.Keywords-DVB, FFT, variable length, scaling, pipelined shared memory. I. INTRODUCTIONOrthogonal frequency division multiplexing (OFDM) attracts much attention in wireless communication systems, because it is feasible to many diverse requirements. In the typical OFDM systems, the complex symbols are modulated by means of inverse fast Fourier transform (IFFT). After guard interval insertion, the resulting OFDM symbol is serially transmitted over various channels, and at the receiver end the data stream is recovered by the inverse operation. Therefore, the FFT and IFFT blocks are the key computational blocks in OFDM systems. The long-size FFT is commonly adopted in OFDM system to increase transmission bandwidth or efficiency in many wireless applications such as digital video broadcasting (DVB), digital audio broadcasting (DAB), digital media broadcasting (DMB), very high-speed digital subscriber line (VDSL) and other mobile applications.The 2k/4k/8k point FFT should be performed in 224µ/448µs/896µs, respectively, according to DVB standards. On designing a long-size FFT processor, one still has to consider its power consumption and hardware cost. Furthermore, the power consumption of both data access in memory and operation of complex multipliers is more than 75% of total power consumption in an FFT processor [1]. To reduce the power consumption of the FFT memories and complex multipliers, the useful method is reducing the memory access times, internal word length and the number of operations in complex multipliers.The memory-based architecture provides lower hardware complexity and high flexibility. However, it has disadvantages

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Section: Performance Evaluation and Comparisonmentioning

confidence: 86%

Low-cost variable-length FFT processor for DVB-T/H applications

Jung

Lee

2010

2010 IEEE Asia Pacific Conference on Circuits and Systems

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“…In the other two, the fully-parallel architecture does not provide any flexibility at all and the pipeline architecture supports only a low degree of reconfigurability on the FFT size. Although some designs are developed for reconfigurable pipeline FFT processors [44,51,48,10,24], their flexibilities are limited only to very few FFT sizes and as a result, the hardware overhead incurred by the reconfigurability is not tolerable for low-power schemes.…”

Section: Overall Structurementioning

confidence: 99%

Improving Energy Efficiency of OFDM Using Adaptive Precision Reconfigurable FFT

Abdoli

Nikmehr

Movahedinia

et al. 2016

Circuits Syst Signal Process

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Being an essential issue in digital systems, especially battery-powered devices, energy efficiency has been the subject of intensive research. In this research, a multi-precision FFT module with dynamic runtime reconfigurability is proposed to trade off accuracy with the energy efficiency of OFDM in an SDR-based architecture. To support variable size FFT, a reconfigurable memory-based architecture is investigated. It is revealed that the radix-4 FFT has the minimum computational complexity in this architecture. Regarding implementation constraints such as fixed-width memory, a noise model is exploited to statistically analyze the proposed architecture. The required FFT word-lengths for different criteria-namely BER, modulation scheme, FFT size, and SNR-are computed analytically and confirmed by simulations in AWGN and Rayleigh fading channels. At run-time, the most energyefficient word-length is chosen and the FFT is reconfigured while the required application-specific BER is met. Evaluations show that the implementation area and the number of memory accesses are reduced. The results obtained

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“…However, those methods are all in radix-q ×2 k FFTs [8], where q is prime, such as 3, 5, and 7, et al Because the mixed radix FFT can be used in general scenarios, it becomes practical and useful. Some mixed radix FFT algorithms are studied, such as radix-2/4 [9,10] and radixFFTs. They are based on radix-2 FFT.…”

Section: Introductionmentioning

confidence: 99%

Simplified addressing scheme for mixed radix FFT algorithms

Xie

Chen

et al. 2014

2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

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A mixed radix algorithm for the in-place fast Fourier transform (FFT), which is broadly used in most embedded signal processing fields, can be explicitly expressed by an iterative equation based on the Cooley-Tukey algorithm. The expression can be applied to either decimation-in-time (DIT) or decimation-in-frequency (DIF) FFTs with ordered inputs. For many newly emerging low power portable computing applications, such as mobile high definition video compressing, mobile fast and accurate satellite location, etc., the existing methods perform either resource consuming or non-flexible. In this paper, we propose a new addressing scheme for efficiently implementing mixed radix FFTs. In this scheme, we elaborately design an accumulator that can generate accessing addresses for the operands, as well as the twiddle factors. The analytical results show that the proposed scheme reduces the algorithm complexity meanwhile helps the designer to efficiently choose an arbitrary FFT to design the in-place architecture.

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Low-cost reconfigurable VLSI architecture for fast fourier transform

Cited by 17 publications

References 10 publications

Low-cost variable-length FFT processor for DVB-T/H applications

Low-cost variable-length FFT processor for DVB-T/H applications

Improving Energy Efficiency of OFDM Using Adaptive Precision Reconfigurable FFT

Simplified addressing scheme for mixed radix FFT algorithms

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