Low-Cost Protection for SER Upsets and Silicon Defects

Abstract

Extreme transistor scaling trends in silicon technology are soon to reach a point where manufactured systems will suffer from limited device reliability and severely reduced life-time, due to early transistor failures, gate oxide wear-out, manufacturing defects, and radiation-induced soft errors (SER). In this paper we present a low-cost technique to harden a microprocessor pipeline and caches against these reliability threats. Our approach utilizes online built-in self-test (BIST) and microarchitectural checkpointing to detect, diagnose and recover the computation impaired by silicon defects or SER events. The approach works by periodically testing the processor to determine if the system is broken. If so, we reconfigure the processor to avoid using the broken component. A similar mechanism is used to detect SER faults, with the difference that recovery is implemented by re-execution. By utilizing low-cost techniques to address defects and SER, we keep protection costs significantly lower than traditional fault-tolerance approaches while providing high levels of coverage for a wide range of faults. Using detailed gate-level simulation, we find that our approach provides 95% and 99% coverage for silicon defects and SER events, respectively, with only a 14% area overhead.

Cardio: CMP Adaptation for Reliability Through Dynamic Introspective Operation

“…(a) Performance overhead of 16 CMP configuration, including between 2 and 32 cores. We considered three different core testing technique: structural testing [30], functional testing [32], and built-in-self-test [50]. (b) and (c) Distinct performance overhead contributions for configurations containing 16 and 32 cores, respectively.…”

“…A number of approaches have been proposed to perform these checks, which vary greatly in fault coverage and cost. In order to measure Cardio's impact with a wide range of hardware self-test solutions, we considered three different techniques: structural testing [30], functional testing [32], and built-in-self-test [50]. Structural and functional test techniques have little impact on the silicon area (up to 6%).…”

“…More silicon real-estate may be required for the core self-test mechanism-between 0% and 15%, depending on the deployed technique [30], [32], [50].…”

Application-Aware diagnosis of runtime hardware faults

“…Hardware-based detection mechanisms insert extra microarchitectural features in order to detect faulty transistors on the chip. For example, Constantinides, et al [5] and Mehrara, et al [11] propose embedding Built-In-Self-Test units and checkers to test the integrity of VLIW processors. These hardware additions account for a significant area overhead, 5.8% and 14%, respectively, and provide limited coverage against permanent faults (89% and 95%).…”

“…Computations are then partitioned into epochs and normal execution is periodically suspended to run a battery of tests on the microprocessor [5]. Periodic testing of microprocessors can be accomplished through the addition of ad-hoc hardware testing components [5,11] and/or through the execution of high-quality software test sequences [4,9]. Even if effective at detecting faults, the execution of online tests is a time consuming task and results in a performance reduction up to 30% [4].…”