Low-Cost and Fast Hardware Implementations of Point Multiplication on Binary Edwards Curves

Rashidi, Bahram

doi:10.1109/icee.2018.8472703

Cited by 13 publications

(23 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Furthermore, the architecture of [22] over GF(P 192 ) requires 868 times higher computation time as compared to our high-performance implementation on Kintex-7 over GF (2 163 ). As compared to the FPGA implementations of [18,[23][24][25][26], our high-performance implementation utilizes lower hardware resources and takes lower computation time for the computation of one PM operation. Our obtained results (for high-performance and power-optimized) make our proposed architecture well-suited for RFID applications.…”

Section: Numerical Flavor Of the Resultsmentioning

confidence: 99%

“…In addition to RFID specific architectures, there are several other PM hardware accelerators, described in [18,[23][24][25][26]. A 2-stage architecture with pipelining to reduce clock cycles and optimize clock frequency is described in [18,24] .…”

Section: Hardware Accelerators For Rfid Applicationsmentioning

confidence: 99%

“…A low-area ECC accelerator architecture using a digit-serial multiplication method is described in [23]. Similar to [21], a low-cost and fast hardware implementations of the PM on Binary Edward-curves is presented in [25]. Moreover, a throughput area architecture to optimize both throughput and area at the same time is provided in [26].…”

Section: Hardware Accelerators For Rfid Applicationsmentioning

confidence: 99%

“…Based on the discussions presented in Section 1.1, it can be observed that the accelerator architectures, published in [14,[18][19][20][21][22][23][24][25][26], are specifically designed to reduce hardware resources (area) and power parameters with the expense of higher clock cycles. Therefore, the increase in clock cycles ultimately reduces the performance of the entire architecture [14,[19][20][21][22].…”

Section: Limitations In Existing Hardware Accelerators Of Rfid Applicationsmentioning

confidence: 99%

“…For a realistic comparison with the state-of-the-art, we have synthesized our proposed architecture in similar devices that have been utilized in recent state-of-the-art publications that include [18,[23][24][25][26].…”

Section: Comparison With Fpga Based Architecturesmentioning

confidence: 99%

See 4 more Smart Citations

Elliptic-Curve Crypto Processor for RFID Applications

et al. 2021

View full text Add to dashboard Cite

This work presents an Elliptic-curve Point Multiplication (ECP) architecture with a focus on low latency and low area for radio-frequency-identification (RFID) applications over GF(2163). To achieve low latency, we have reduced the clock cycles by using: (i) three-shift buffers in the datapath to load Elliptic-curve parameters as well as an initial point, (ii) the identical size of input/output interfaces in all building blocks of the architecture. The low area is preserved by using the same hardware resources of squaring and multiplication for inversion computation. Finally, an efficient controller is used to control the inferred logic. The proposed ECP architecture is modeled in Verilog and the synthesis results are given on three different 7-series FPGA (Field Programmable Gate Array) devices, i.e., Kintex-7, Artix-7, and Virtex-7. The performance of the architecture is provided with the integration of a schoolbook multiplier (implemented with two different logic styles, i.e., combinational and sequential). On Kintex-7, the combinational implementation style of a schoolbook multiplier results in power-optimized, i.e., 161 μW, values with an expense of (i) hardware resources, i.e., 3561 look-up-tables and 1527 flip-flops, (ii) clock frequency, i.e., 227 MHz, and (iii) latency, i.e., 11.57 μs. On the same Kintex-7 device, the sequential implementation style of a schoolbook multiplier provides, (i) 2.88 μs latency, (ii) 1786 look-up-tables and 1855 flip-flops, (iii) 647 μW power, and (iv) 909 MHz clock frequency. Therefore, the reported area, latency and power results make the proposed ECP architecture well-suited for RFID applications.

show abstract

Section: Numerical Flavor Of the Resultsmentioning

confidence: 99%

Section: Hardware Accelerators For Rfid Applicationsmentioning

confidence: 99%

Section: Hardware Accelerators For Rfid Applicationsmentioning

confidence: 99%

Section: Limitations In Existing Hardware Accelerators Of Rfid Applicationsmentioning

confidence: 99%

Section: Comparison With Fpga Based Architecturesmentioning

confidence: 99%

See 3 more Smart Citations

Elliptic-Curve Crypto Processor for RFID Applications

et al. 2021

View full text Add to dashboard Cite

show abstract

Efficient hardware implementations of point multiplication for binary Edwards curves

Rashidi

2018

Circuit Theory & Apps

View full text Add to dashboard Cite

SummaryThis paper presents efficient and fast hardware implementations of the complete point multiplication on binary Edwards curves (BECs). The implementations are based on extremely fast complete differential addition and doubling formulas. These new complete differential addition formulas are performed for general and special cases of BECs with cost of 5M + 4S + 2D and 5M + 4S + 1D, respectively, where, M, S, and D denote the costs of a field multiplication, a field squaring and a field multiplication by a constant, respectively. In the general case of the BECs, proposed structures are implemented based on 3 and 1 pipelined digit‐serial Gaussian normal basis multipliers. In the design by 3 multipliers, computation of point addition and point doubling is performed concurrently. But in the second implementation for low‐cost design with low number of hardware resources, these computations are implemented by 1 multiplier. Also, in the special case of BECs, 2 structures are proposed for achieving the highest degree of parallelization and utilization of resources by using 3 and 2 field multipliers. Implementation results of the proposed architectures based on Virtex‐5 XC5VLX110, Virtex‐4 XC4VLX100, and Arria‐10 10AX115U4F45I3SG FPGAs for 2 fields and are achieved. The results show improvements in terms of execution time, area, and efficiency for the proposed structures compared with previous works.

show abstract

Full‐custom hardware implementation of point multiplication on binary Edwards curves for application‐specific integrated circuit elliptic curve cryptosystem applications

Rashidi

Sayedi

Farashahi

2017

IET Circuits, Devices & Syst

Self Cite

View full text Add to dashboard Cite

This study presents an efficient and high-speed very large-scale integration implementation of point multiplication on binary Edwards curves over binary finite field GF(2 m) with Gaussian normal basis representation. The proposed implementation is a low-cost structure constructed by one digit-serial multiplier. In the proposed scheduling of point multiplication, the field multiplier is busy during point addition and point doubling computations. In the field multiplier structure, by using the logical effort technique the delay is optimally decreased and the drive ability of the circuit in the point multiplication architecture is increased. Also, to reduce area and number of transistors of the point multiplication circuit, all components are selected based on low-cost structures. The design is implemented in 0.18 μm CMOS technology over binary finite field GF(2 233). The results confirm the validity of the proposed structure and its high performance in terms of delay and area cost.

show abstract

Low-Cost and Fast Hardware Implementations of Point Multiplication on Binary Edwards Curves

Cited by 13 publications

References 21 publications

Elliptic-Curve Crypto Processor for RFID Applications

Elliptic-Curve Crypto Processor for RFID Applications

Efficient hardware implementations of point multiplication for binary Edwards curves

Full‐custom hardware implementation of point multiplication on binary Edwards curves for application‐specific integrated circuit elliptic curve cryptosystem applications

Contact Info

Product

Resources

About