Low Complexity Neural Network-Aided NMS LDPC Decoder

Shi, Honghao; Zhong, Mingyang; Luo, Zhiyong; Li, Congduan

doi:10.1109/comcomap53641.2021.9652964

Cited by 5 publications

(4 citation statements)

References 11 publications

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“…There is no information about the implementation of this decoder, but it is clear that its BER performance lags behind our decoder by almost 2 dB. The decoder of [ 39 ] uses CCSDS (8176, 7154) LDPC with code rate 7/8, performing 20 iterations, the decoding algorithm used is NMS, and the encoding and decoding process are both unquantized. Its BER achieves

a Eb/N0 of 3.9.…”

Section: Resultsmentioning

confidence: 99%

Design and Implementation of a Highly Efficient Quasi-Cyclic Low-Density Parity-Check Transceiving System Using an Overlapping Decoder

Sun,

Zhao,

et al. 2023

Sensors

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The traditional LDPC encoding and decoding system is characterized by low throughput and high resource consumption, making it unsuitable for use in cost-efficient, energy-saving sensor networks. Aiming to optimize coding complexity and throughput, this paper proposes a combined design of a novel LDPC code structure and the corresponding overlapping decoding strategies. With regard to structure of LDPC code, a CCSDS-like quasi-cyclic parity check matrix (PCM) with uniform distribution of submatrices is constructed to maximize overlap depth and adapt the parallel decoding. In terms of reception decoding strategies, we use a modified 2-bit Min-Sum algorithm (MSA) that achieves a coding gain of 5 dB at a bit error rate of 10−6 compared to an uncoded BPSK, further mitigating resource consumption, and which only incurs a slight loss compared to the standard MSA. Moreover, a shift-register-based memory scheduling strategy is presented to fully utilize the quasi-cyclic characteristic and shorten the read/write latency. With proper overlap scheduling, the time consumption can be reduced by one third per iteration compared to the non-overlap algorithm. Simulation and implementation results demonstrate that our decoder can achieve a throughput up to 7.76 Gbps at a frequency of 156.25 MHz operating eight iterations, with a two-thirds resource consumption saving.

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a Eb/N0 of 3.9.…”

Section: Resultsmentioning

confidence: 99%

Design and Implementation of a Highly Efficient Quasi-Cyclic Low-Density Parity-Check Transceiving System Using an Overlapping Decoder

Sun,

Zhao,

et al. 2023

Sensors

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show abstract

“…Although the MS decoder requires fewer computations, the approximated results always have a greater absolute value than those of BP, which causes performance degradation. To mitigate performance loss, the normalized min-sum (NMS) scheme [21] and its variant were studied [22]; moreover, a neural network-aided NMS approach was proposed in [23]. The BP decoding scheme can be described as Algorithm 1.…”

Section: Ldpc and Rs Codementioning

confidence: 99%

“…By recursively applying (22), R n (k + 4) is determined by five variable terms: R n−4 (k) (except for R 0 , R 1 , R 2 , R 3 ), (d k + R 19 (k)), (d k+1 + R 18 (k)), (d k+2 + R 17 (k)), and (d k+3 + R 16 (k)). We take R 5 (k + 4) for example, as in (23), which is clearly especially complicated to derive and difficult to understand. In order to simplify the derivation, we came up with an easy approach for calculating parallel encoding coefficients, leveraging a conventional serial encoder structure.…”

Section: Rs Parallel Encodermentioning

confidence: 99%

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An LDPC-RS Concatenation and Decoding Scheme to Lower the Error Floor for FTN Signaling

Shi,

Luo,

2024

Electronics

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Faster-than-Nyquist (FTN) signaling has attracted increasing interest in the past two decades. However, when the fifth-generation (5G) communication low-density parity check (LDPC) code is applied to FTN signaling with low Bahl–Cock–Jelinek–Raviv (BCJR) states of detection and few turbo equalization iterations, an error floor near 10−5 is found, which does not exist in the original LDPC used for orthogonal signaling. This can be eliminated through many detection and decoding iterations, but this is unacceptable considering the increase in latency and storage. To solve this problem, we propose an LDPC and Reed–Solomon (RS) concatenation code, shortening, and perturbation scheme to lower the error floor. We propose a parallel encoder architecture for RS component code and a concise algorithm to calculate its constant multiplier coefficients, leveraging a traditional serial encoder, which can also be used for other parallelisms, rates, and lengths. The simulation results show that the proposed concatenation and shortening scheme can lower the error floor to about 10−7. The proposed scheme has an error correction capability for coded FTN signaling and successfully lowers the error floor with the limitation of few turbo iterations and few BCJR states.

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A Model-Driven Quasi-ResNet Belief Propagation Neural Network Decoder for LDPC Codes

Ma,

Liu,

et al. 2023

2023 IEEE Symposium on Computers and Communications (ISCC)

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Low Complexity Neural Network-Aided NMS LDPC Decoder

Cited by 5 publications

References 11 publications

Design and Implementation of a Highly Efficient Quasi-Cyclic Low-Density Parity-Check Transceiving System Using an Overlapping Decoder

Design and Implementation of a Highly Efficient Quasi-Cyclic Low-Density Parity-Check Transceiving System Using an Overlapping Decoder

An LDPC-RS Concatenation and Decoding Scheme to Lower the Error Floor for FTN Signaling

A Model-Driven Quasi-ResNet Belief Propagation Neural Network Decoder for LDPC Codes

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