Low-Complexity Loeffler DCT Approximations for Image and Video Coding

Coelho, Diego F. G.; Cintra, Renato J.; Bayer, Fábio M.; Kulasekera, Sunera; Madanayake, Arjuna; Martinez, Paulo; Silveira, Thiago L. T. da; Oliveira, Rodrigo Silva de; Dimitrov, Vassil S.

doi:10.3390/jlpea8040046

Cited by 12 publications

(12 citation statements)

References 61 publications

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“…N can be represented according to the polar decomposition [53, p. 348] consisting of two parts: (i) a low-complexity matrix T N and (ii) a diagonal matrix Σ N that provides orthogonalization or quasi-orthogonalization [39,53]. Such matrices are related according to:…”

Section: In General a Dct-ii Approximation ĉIimentioning

confidence: 99%

“…and • is the matrix square root [53]. Here the operator diag( • ) returns a diagonal matrix with the elements of the diagonal of its matrix argument [39,53].…”

Section: In General a Dct-ii Approximation ĉIimentioning

confidence: 99%

“…Because it is often an analytically intractable problem, exhaustive search and brute force calculations are commonly adopted as solution methods [37,38]. For small blocklengths, such as N = 8, the exhaustive search approach is effective and led to the proposition of several low-complexity approximations for the DCT-II [39,40]. On the other hand, as N increases, the number of variables increases quadratically, which leads to large computation times; thus becoming an impractical approach.…”

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confidence: 99%

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Low-complexity Scaling Methods for DCT-II Approximations

Coelho,

Cintra,

Madanayake

et al. 2021

Preprint

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This paper introduces a collection of scaling methods for generating 2N-point DCT-II approximations based on N-point low-complexity transformations. Such scaling is based on the Hou recursive matrix factorization of the exact 2N-point DCT-II matrix. Encompassing the widely employed Jridi-Alfalou-Meher scaling method, the proposed techniques are shown to produce DCT-II approximations that outperform the transforms resulting from the JAM scaling method according to total error energy and mean squared error. Orthogonality conditions are derived and an extensive error analysis based on statistical simulation demonstrates the good performance of the introduced scaling methods. A hardware implementation is also provided demonstrating the competitiveness of the proposed methods when compared to the JAM scaling method.

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Section: In General a Dct-ii Approximation ĉIimentioning

confidence: 99%

“…and • is the matrix square root [53]. Here the operator diag( • ) returns a diagonal matrix with the elements of the diagonal of its matrix argument [39,53].…”

Section: In General a Dct-ii Approximation ĉIimentioning

confidence: 99%

mentioning

confidence: 99%

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Low-complexity Scaling Methods for DCT-II Approximations

Coelho,

Cintra,

Madanayake

et al. 2021

Preprint

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“…x 16u = x 8u x 8d (13) x 8u = C 8e Z 8e + C 8o Z 8o = a + b (14) x 8d = C 8e Z 8e − C 8o Z 8o = a − b (15) and…”

Section: Y = Czc Tunclassified

A low-area high-efficiency video coding inverse transform core using resource and time sharing architecture

Chen

Liu

2020

EURASIP J. Adv. Signal Process.

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In this paper, a very-large-scale integration (VLSI) design that can support high-efficiency video coding inverse discrete cosine transform (IDCT) for multiple transform sizes is proposed. The proposed two-dimensional (2-D) IDCT is implemented at a low area by using a single one-dimensional (1-D) IDCT core with a transpose memory. The proposed 1-D IDCT core decomposes a 32-point transform into 16-, 8-, and 4-point matrix products according to the symmetric property of the transform coefficient. Moreover, we use the shift-and-add unit to share hardware resources between multiple transform dimension matrix products. The 1-D IDCT core can simultaneously calculate the first- and second-dimensional data. The results indicate that the proposed 2-D IDCT core has a throughput rate of 250 MP/s, with only 110 K gate counts when implemented into the Taiwan semiconductor manufacturing (TSMC) 90-nm complementary metal-oxide-semiconductor (CMOS) technology. The results show the proposed circuit has the smallest area supporting the multiple transform sizes.

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“…In fact, the largest coding unit in HEVC can be up to 64 × 64 in size, and the Transform Unit (TU) sizes can be 4 × 4, 8 × 8, 16 × 16, and 32 × 32 [10]. This multiple TU sizes improve the compression performance but increase the computational complexity to reach a real-time execution [11,12]. In this context, based on the complexity analysis of the HEVC decoder modules for all-intra configuration performed in [13], we can notice that the entropy decoding (ED), the intra prediction (IP) and the DE/IT modules consume on average 38%, 32% and 20% of the total decoding time, respectively.…”

Section: Introductionmentioning

confidence: 99%

Unified FPGA Design for the HEVC Dequantization and Inverse Transform Modules

Alanazi¹,

Atitallah²

2022

Computers, Materials &Amp; Continua

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As the newest standard, the High Efficiency Video Coding (HEVC) is specially designed to minimize the bitrate for video data transfer and to support High Definition (HD) and ULTRA HD video resolutions at the cost of increasing computational complexity relative to earlier standards like the H.264. Therefore, real-time video decoding with HEVC decoder becomes a challenging task. However, the Dequantization and Inverse Transform (DE/IT) are one of the computationally intensive modules in the HEVC decoder which are used to reconstruct the residual block. Thus, in this paper, a unified hardware architecture is proposed to implement the HEVC DE/IT module for all Transform Unit (TU) block size, including 4 × 4, 8 × 8, 16 × 16 and 32 × 32. This architecture is designed using the High-Level Synthesis (HLS) and the Low-Level Synthesis (LLS) methods in order to compare and determine the best method to implement in real-time the DE/IT module. In fact, the C/C++ programming language is used to generate an optimized hardware design for DE/IT module through the Xilinx Vivado HLS tool. On the other hand, the LLS hardware architecture is designed by the VHSIC Hardware Description language (VHDL) and using the pipeline technique to decrease the processing time. The experimental results on the Xilinx XC7Z020 FPGA show that the LLS design increases the throughput in term of frame rate by 80% relative to HLS design with a 4.4% increase in the number of Look-Up Tables (LUTs). Compared with existing related works in literature, the proposed architectures demonstrate significant advantages in hardware cost and performance improvement.

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Low-Complexity Loeffler DCT Approximations for Image and Video Coding

Cited by 12 publications

References 61 publications

Low-complexity Scaling Methods for DCT-II Approximations

Low-complexity Scaling Methods for DCT-II Approximations

A low-area high-efficiency video coding inverse transform core using resource and time sharing architecture

Unified FPGA Design for the HEVC Dequantization and Inverse Transform Modules

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