Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication

Abstract

This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.

LDPC Decoder Design Using Compensation Scheme of Group Comparison for 5G Communication Systems

“…Because it achieves 33.2 Gb/s/iteration using the TSMC 28 nm CMOS process, the throughput rates are 6.64 Gb/s at average iterations of 5, and 7.92 Gb/s at average iterations of 4.92, for the rate-1/3 BG 1 and rate-1/2 BG2 LDPC decoding, respectively. Compared to [23,24], the proposed dual-mode decoder using the layered INPMSA decoding achieves a high throughput of 10.86 Gb/s, which meets the requirement of 5G NR application with a high NAE of 11.40 bits/mm 2 and low NEE of 28.85 pJ/bit. This reveals that the INPMSA using the proposed compensation scheme achieves a low silicon area with low energy consumption.…”

“…Table 3 also lists a comparison of recent studies for the 5G NR systems. The studies in [23,24] achieved post-layout and post-synthesis (prelayout) implementations, respectively. Compared to the post-synthesis implementation, the post-layout implementation contains more hardware information, including the logic gate placements, clock tree synthesis, and wire routing.…”

“…Compared to the post-synthesis implementation, the post-layout implementation contains more hardware information, including the logic gate placements, clock tree synthesis, and wire routing. It is worth noting that the studies in [23,24] focused on the low code-rate (high correcting ability) LDPC decoding and this study focused on the high code-rate (high transmission rate) LDPC decoding for the 5G NR systems. Thus, it is hard to compare these application-specific integrated circuits (ASICs) because their design parameters are very district.…”

“…The NEE denotes how much energy per decoded bit is consumed in the decoder. In early 2021, the study in [23] proposed the LDPC decoder ASIC for the 5G NR standard using a layered combination min-sun algorithm (CMSA) decoding to achieve the features of low complexity and high throughput. It supports a low rate-1/3 BG 1 with a code length of 3808.…”

Some variations of Tanner's construction for short length QC‐LDPC codes

“…Quasi‐cyclic low‐density parity‐check (QC‐LDPC) codes are a family of LDPC codes that exhibit a property: cyclically shifting a codeword for some fixed integer number of times produces another valid codeword. This property makes QC‐LDPC codes an attractive option for high‐speed communication systems, as they enable simple encoding methods with low required memory [6, 7] and low complexity decoding techniques [8].…”