Low Complexity High Quality Fractional Motion Estimation Algorithm and Architecture Design for H.264/AVC

Tan

2010 IEEE International Conference on Multimedia and Expo

et al. 2010

Self Cite

Fractional motion estimation (FME) searches subpixels for blocks of various sizes to find out the best matching candidate, which improves the compression efficiency but leads to high computational complexity. In this paper, we propose a low complexity FME design supporting adaptive mode selection (AMS). Exploiting both the mode correlation among neighboring macroblocks and integer motion estimation result, we can select FME modes adaptively to reduce complexity with good video quality. The simulation result shows that the average number of processing modes in FME is reduced to be 2 for HD1080 video instead of processing 7 modes in JM reference software. With tiny PSNR drop (~0.026dB), the proposed design achieves 71% reduction in computational complexity when compared to JM14.2. At operating frequency of 300MHz, the proposed design could support the real-time processing for H.264 videos with resolution up to 4K x 2K.

Section: Consideration For Hardware Realizationmentioning

confidence: 99%

Low complexity fractional motion estimation with adaptive mode selection for H.264/AVC

Tan

2010 IEEE International Conference on Multimedia and Expo

et al. 2010

Self Cite

Proceedings of the 44th Annual Conference on Design Automation - DAC '07

“…It performs block-matching algorithm between successive frames to determine a motion vector (MV) for each MB in the current frame, and then obtains the residual data to be compressed. First of all, we adopt our low complexity, high quality fast algorithms for H.264 IME and FME by reducing over 90% of complexity as compared to the full search ME algorithms adopted in JM9.7 [13,14]. The key operation, i.e.…”

Section: Motion Estimationmentioning

confidence: 99%

An embedded coherent-multithreading multimedia processor and its programming model

Chu

Chou

et al. 2007

Self Cite

Multithreading and multi-core processing have been shown to be powerful approaches for boosting a system performance by taking advantage of parallelism in applications. This paper presents a processor design by unifying RISC and multithreading DSP for the sophisticated multimedia applications with advanced standards such as H.264. The proposed design not only minimizes integration costs for embedded multithreading/multi-core design by independent coherent threads, but also reduces the memory bandwidth requirements by one-stop streaming buffer and a very fast data exchange mechanism. With the proposed techniques and appropriate programming model, we can achieve 78% reduction of memory bandwidth and 89% reduction of processing time in H.264 video encoding, compared to traditional single stream micro-processor.

2008 IEEE International Conference on Multimedia and Expo

“…The single iteration approach halves the cycle counts while the six point scheme saves about 20% of area at the expense of about 25% bitrate increasing. Reference [5] proposes a mode reduction scheme that reduces 30% of hardware cost at the expense of about 0.13dB PSNR drop.…”

Section: Introductionmentioning

confidence: 99%

A high performance three-engine architecture for H.264/AVC fractional motion estimation

Kao

Lin

2008

Multiple-reference-frame, quarter-pixel accuracy, and variable-block-size motion estimation (VBSME) employed in H.264/AVC is one of the major contributors to its outstanding compression efficiency and video quality. However, due to its high computational complexity, VBSME needs acceleration for real-time application. We propose a high throughput hardware architecture for H.264/AVC fractional motion estimation (FME). The proposed architecture consists of three parallel processing engines. In addition, we propose a resource sharing method which leads to 50% hardware saving in the computation sum of absolute transformed difference (SATD). Synthesized into a TSMC 130nm CMOS cell library, our design takes 311.7K gates at 154MHz and can encode 1080pHD video at 30 frames per second (fps). Compared to previous works, the proposed design runs at much lower frequency for the same resolution and frame rate. IndexTerms-H.264/AVC, fractional motion estimation, very large-scale integration (VLSI) architecture