Low Area and Power-Efficient FPGA Implementation of Improved AM-CSA-IIR Filter Design for the DSP Application

Abstract

Digital Signal Processing (DSP) grew enormously in the past few decades and it was extensively practiced for numerous engineering applications like biomedical signal processing, radar signal processing, adaptive antenna design, intelligent control, etc. In DSP, the Finite Impulse Response (FIR) filter and Infinite Impulse Response (IIR) filter plays a vital role in the design of a complex signal processing system. Generally, The FIR filters are stable, linear in phase, with fewer finite-precision errors and easy to implement. However, most of the IIR filters are used in signal processing applications due to the less computational complexity which is compared to the FIR filters. Moreover, the IIR filter requires only fewer filter coefficients and requires only less amount storage registers. In this research, an IIR filter is implemented with Array multiplier and Carry Skip Adder (CSA) to improve hardware utilization. The IIR filter input is generated randomly which is stored in Random Access Memory (RAM). Similarly, the coefficient is generated by utilizing the Parks-McClellan algorithm where the generated value is stored in Read Only Memory (ROM). The proposed AM-CSA IIR (Array Multiplier-Carry Skip Adder Infinite Impulse Response) filter performances are evaluated in terms of filter output, Input Output Block (IOB), Look Up Table (LUT), Flip Flops (FF), slices, delay, and fractional delay. Overall the proposed design attained LUT= 115 (0.0564%), FF=40 (0.01%) and IOB= 22 (3.77%) and reduced fractional delay of about 0.0057ns.