Low area and high throughput hardware implementations for the LILLIPUT cipher

Abstract

SummaryThe widespread use of Internet of Things devices has increased the demand for lower cost and more efficient lightweight ciphers. However, there is a difficult trade‐off between cost and efficiency for lightweight block ciphers. The optimizations of area and throughput are important for some constrained environments. This paper proposes two novel hardware architectures for the LILLIPUT cipher. In the novel low area structure, a new permutation layer is provided for LILLIPUT. The relationship between encryption algorithm and key scheduling algorithm is utilized to achieve optimal sharing among components, which significantly reduces hardware area. The experimental results show that the number of XOR gates and S‐boxes required for low area optimization is reduced by 52 and 8, respectively. The total area is reduced by about 18%. For high throughput structure, this paper provides 2‐round, 5‐round, and 15‐round loop unrolling designs for LILLIPUT to improve throughput. The experimental results show that the throughput of the 5‐round loop unrolling structure reaches a good level, which is relatively the most cost‐effective. In practical application, ciphers can be unrolled implementations according to the needs of devices to improve the execution speed, which can greatly reduce the execution time and complexity of the algorithm.