Abstract::
This work reviews the design challenges of CMOS flash type Analog-to-Digital Converter
(ADC) for making high bit resolution, low area, low noise, low offset, and power-efficient architecture.
Low-bit resolution flash ADC architecture, high-speed applications, and wide-area parallel comparators
are identified on their suitability of the design for ADCs. These are effective in the area and bit resolution.
The overview includes bit resolution, area, power dissipation, bandwidth and offset noise consideration
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