Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs

Liang, Joshua; Sheikholeslami, Ali; Tamura, Hirotaka; Ogata, Yudai; Yamaguchi, Hisakatsu

doi:10.1109/jssc.2018.2839038

Cited by 19 publications

(7 citation statements)

References 18 publications

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“…In order to simulate the loop performance of MM-CDR, MMPD needs to be linearized. Refer to other works focused on the process of BBPD linearization [4][5][6][7]. The ideal non-linear output of the MMPD will be smoothed due to the presence of the actual jitter in the input signal and recovery clock, which makes the output response of the MMPD can be linearized within a certain input range.…”

Section: Linearization Of Mmpdmentioning

confidence: 99%

Analysis of Mueller-Muller Clock and Data Recovery Circuits with a Linearized Model

Feng

Chi

et al. 2022

Preprint

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With the development of high-speed analog-to-digital converter (ADC) based wireline receivers, Mueller-Muller clock and data recovery (MM-CDR) circuit also get more and more attention. But in the design stage, the MM-CDR circuit used in ADC-based wireline receiver is difficult to evaluate its loop performance, owing to the lack of linearized model of Mueller-Muller phase detector (MMPD). In this paper, by analyzing the slope and distribution of the signal at different positions, a linearized model of MMPD is proposed and the model is combined with an entire MM-CDR system to analyze the performance of the MM-CDR loop. Through the analysis of the linearized model and the verification of the actual simulation, we can know that when the VREF level in the MMPD is set equal to the amplitude of the main-cursor h0, the MMPD can obtain the maximum gain, and the jitter transfer function and jitter tolerance can achieve optimum performance.

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Section: Linearization Of Mmpdmentioning

confidence: 99%

Analysis of Mueller-Muller Clock and Data Recovery Circuits with a Linearized Model

Feng

Chi

et al. 2022

Preprint

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“…In Fig. 5 to extract K E F F the following set of expressions from [9], [10] and [11] has been used in conjunction with the nonlinear simulation results:…”

Section: Dpc Modellingmentioning

confidence: 99%

A 7-Bit 7-GHz Multiphase Interpolator-Based DPC for CDR Applications

Khanghah¹,

Sadeghipour²,

Kelly³

et al. 2022

IEEE Trans. Circuits Syst. I

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This paper presents a 7-bit digital to phase converter (DPC) for high speed clock and data recovery (CDR) applications which is capable of generating multi-phase clocks at 7-GHz frequency. Fabricated in a standard 65-nm CMOS technology, the design introduces a modified phase interpolator (PI) and a quadrature phase corrector (QPC) to reduce the effect of the circuit imperfections on the DPC's resolution and linearity. Employing a 14-GHz quadrature reference clock, the DPC achieves DNL/INL of 0.7/6 LSB respectively while consuming 40.5 mW power from 1.05 V supply. Index Terms-Digital to phase converter (DPC), clock and data recovery (CDR), phase interpolator (PI), wireline and optical communication.

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“…The jitter tolerance is the maximum amount of input jitter that can be tolerated by the clock and data recovery circuit at a given bit error rate (BER) [15]. Therefore, the jitter tolerance computed by (17) for a target BER is 10 −10 .…”

Section: Linearized Analysis Of Cdr Systemmentioning

confidence: 99%

“…In contrast, if we estimate the error jitter in advance based on the circuit characteristics, we can not only obtain accurate CDR performance metrics, but also shorten the design cycle. Here, we focus on the effect of the two main sources of jitter on the error jitter: input data jitter and PI quantization noise [17].…”

Section: Jitter Analysis Of Mm-cdrmentioning

confidence: 99%

Analysis and Modeling of Mueller–Muller Clock and Data Recovery Circuits

Liu

et al. 2021

Electronics

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In this paper, an accurate linear model of the Mueller–Muller phase detector (MMPD)-based clock and data recovery circuit (MM-CDR) is proposed, which analyzes several critical points of the MM-CDR including the linearization of the MMPD and the gain of the voter. Using our technique, the jitter between the recovery clock and the input data can be estimated with a sub-picosecond accuracy, as demonstrated in the simulation results of a 56 Gb/s quarter-rate MM-CDR implemented in 28 nm CMOS.

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Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs

Cited by 19 publications

References 18 publications

Analysis of Mueller-Muller Clock and Data Recovery Circuits with a Linearized Model

Analysis of Mueller-Muller Clock and Data Recovery Circuits with a Linearized Model

A 7-Bit 7-GHz Multiphase Interpolator-Based DPC for CDR Applications

Analysis and Modeling of Mueller–Muller Clock and Data Recovery Circuits

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