Look-Up Table based Energy Efficient Processing in Cache Support for Neural Network Acceleration

Ramanathan, Akshay Krishna; Kalsi, Gurpreet S.; Srinivasa, Srivatsa; Chandran, Tarun Makesh; Pillai, Kamlesh; Omer, Om Ji; Narayanan, Vijaykrishnan; Subramoney, Sreenivas

doi:10.1109/micro50266.2020.00020

Cited by 29 publications

(7 citation statements)

References 42 publications

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“…Based on this observation, we can reduce the number of storage entries using two-step optimization. In the first optimization step, we remove the even part of the LUT input data pair as described in [ 38 ]. The multiplication of even data and of other data (odd or even) includes two cases: ❶ It is decomposed into the multiplication of two odd numbers, and the multiplication result is then shifted to obtain the final result.…”

Section: Efficient Search-based Computing Schemementioning

confidence: 99%

SCA: Search-Based Computing Hardware Architecture with Precision Scalable and Computation Reconfigurable Scheme

Chang

Zhao

Zhou

2022

Sensors

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Deep neural networks have been deployed in various hardware accelerators, such as graph process units (GPUs), field-program gate arrays (FPGAs), and application specific integrated circuit (ASIC) chips. Normally, a huge amount of computation is required in the inference process, creating significant logic resource overheads. In addition, frequent data accessions between off-chip memory and hardware accelerators create bottlenecks, leading to decline in hardware efficiency. Many solutions have been proposed to reduce hardware overhead and data movements. For example, specific lookup-table (LUT)-based hardware architecture can be used to mitigate computing operation demands. However, typical LUT-based accelerators are affected by computational precision limitation and poor scalability issues. In this paper, we propose a search-based computing scheme based on an LUT solution, which improves computation efficiency by replacing traditional multiplication with a search operation. In addition, the proposed scheme supports different precision multiple-bit widths to meet the needs of different DNN-based applications. We design a reconfigurable computing strategy, which can efficiently adapt to the convolution of different kernel sizes to improve hardware scalability. We implement a search-based architecture, namely SCA, which adopts an on-chip storage mechanism, thus greatly reducing interactions with off-chip memory and alleviating bandwidth pressure. Based on experimental evaluation, the proposed SCA architecture can achieve 92%, 96% and 98% computational utilization for computational precision of 4 bit, 8 bit and 16 bit, respectively. Compared with state-of-the-art LUT-based architecture, the efficiency can be improved four-fold.

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Section: Efficient Search-based Computing Schemementioning

confidence: 99%

SCA: Search-Based Computing Hardware Architecture with Precision Scalable and Computation Reconfigurable Scheme

Chang

Zhao

Zhou

2022

Sensors

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“…NDPproposals have explored many memory architectures. In the literature, SRAM-based NDP proposals mostly aim to insert logic capabilities to the host's cache memories or to the host's memory controllers [17,19,20,21,22,23,24,58,59,103,106]. This work modify the cache hierarchy trying to avoid moving data from the main memory and cache memories to the host's core.…”

Section: B Memory Architectures and Ndpmentioning

confidence: 99%

“…Yin et al [21] part from the same base idea as Neural Cache, but enable more scalability by using XNOR-Accumulate operations to enable activation of multiple SRAM rows, double buffers to hide in-memory reprogramming latencies, and additional peripheral logic for multi-bit activation. Ramanathan et al [22] propose the BFree, a bit-line free LUTbased NDP in SRAM subarrays that allows reconfigurable precision and NN layout. Long et al [23] further optimize NN for these architectures, showcasing their potential for practical usage with LeNet, AlexNet, VGGNet, and ResNet Convolutional Neural Network (CNN) architectures.…”

Section: Introductionmentioning

confidence: 99%

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Survey on Near-Data Processing: Applications and Architectures

Santos

Moreira

Cordeiro

et al. 2021

JICS

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One of the main challenges for modern processors is the data transfer between processor and memory. Such data movement implies high latency and high energy consumption. In this context, Near-Data Processing (NDP) proposals have started to gain acceptance as an accelerator device. Such proposals alleviate the memory bottleneck by moving instructions to data whereabouts. The first proposals date back to the 1990s, but it was only in the 2010s that we could observe an increase in papers addressing NDP. It occurred together with the appearance of 3D-stacked chips with logic and memory stacked layers. This survey presents a brief history of these accelerators, focusing on the applications domains migrated to near-data and the proposed architectures. We also introduce a new taxonomy to classify such architectural proposals according to their data distance.

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“…The look-up table (LUT)-based CIM architecture is proposed to solve the issue of mixed-based CIM solution [47]. In LUT-based CIM, two memory rows are designed for LUT, supporting two modes: storage and computation modes.…”

Section: Cim Architecture Beyond Mixed Solutionmentioning

confidence: 99%

Energy-efficient computing-in-memory architecture for AI processor: device, circuit, architecture perspective

Chang

Zhang

et al. 2021

Sci. China Inf. Sci.

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An artificial intelligence (AI) processor is a promising solution for energy-efficient data processing, including health monitoring and image/voice recognition. However, data movements between compute part and memory induce memory wall and power wall challenges to the conventional computing architecture. Recently, the memory-centric architecture has been revised to solve the data movement issue, where the memory is equipped with the compute-capable memory technique, namely, computing-in-memory (CIM). In this paper, we analyze the requirement of AI algorithms on the data movement and low power requirement of AI processors. In addition, we introduce the story of CIM and implementation methodologies of CIM architecture. Furthermore, we present several novel solutions beyond traditional analog-digital mixed static random-access memory (SRAM)-based CIM architecture. Finally, recent CIM tape-out studies are listed and discussed.

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Look-Up Table based Energy Efficient Processing in Cache Support for Neural Network Acceleration

Cited by 29 publications

References 42 publications

SCA: Search-Based Computing Hardware Architecture with Precision Scalable and Computation Reconfigurable Scheme

SCA: Search-Based Computing Hardware Architecture with Precision Scalable and Computation Reconfigurable Scheme

Survey on Near-Data Processing: Applications and Architectures

Energy-efficient computing-in-memory architecture for AI processor: device, circuit, architecture perspective

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