Look-ahead mapping of Boolean functions in memristive crossbar array

Yadav, Dev Narayan; Thangkhiew, Phrangboklang Lyngton; Datta, Kamalika

doi:10.1016/j.vlsi.2018.10.001

Cited by 30 publications

(18 citation statements)

References 17 publications

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“…CNIMP (or IMPLY) and MAGIC mapping has been covered in some works, e.g. in [33] and [34]. They rely on the capability of parallel row and column-wise operations of NOR and NOT gates and propose optimizing algorithms for faster, less consuming area and power consuming logic realizations.…”

Section: Ratioed Logic With Memristorsmentioning

confidence: 99%

Memristive Logic in Crossbar Memory Arrays: Variability-Aware Design for Higher Reliability

Escudero

Vourkas

Rubio

et al. 2019

IEEE Trans. Nanotechnology

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The advent of the first TiO2-based memristor in 2008 revived the scientific interest both from academia and industry for this device technology and has so far led to several emerging applications including logic and in-memory computing. Several memristive logic families have been proposed in the current quest for energy-efficient future computing systems. However, the limited device endurance and variability (both cycleto-cycle and device-to-device) are important parameters to be considered in the assessment of logic operations. In this work we used an accurate physics-based model of a bipolar memristor (supporting parasitics of the device structure and variability of switching voltages and resistance states) and demonstrate that performance of memristor-based in-memory computations can de degraded owing to both variability and state drift impact, if such features are not properly considered in the design flow. Inspired on pseudo-NMOS ratioed logic and based upon a CMOS-like logic scheme, we propose a crossbar-compatible memristive ratioed logic style which is tolerant to device variability and does not affect device endurance as computations do not involve conditional switching of memristors. Using the Cadence Virtuoso suite, we compare this logic scheme with MAGIC and CNIMP approaches, focusing on the universal NOR gate and complex logic functions.

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Section: Ratioed Logic With Memristorsmentioning

confidence: 99%

Memristive Logic in Crossbar Memory Arrays: Variability-Aware Design for Higher Reliability

Escudero

Vourkas

Rubio

et al. 2019

IEEE Trans. Nanotechnology

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show abstract

“…The netlists we use consist of N-input NOR gates, where either: (1) N ∈ {1, 2}, i.e., NOT gates and two-input NOR gates (N OR2), or (2) N ∈ {1, 2, 3, 4} (N OR4). The evaluation consists of three parts: 1) Comparison to other mapping tools: SIMPLE MAGIC [23], Yadav et al [24] (referred as YADAV for the rest of the paper) and SAID [25]. For each comparison, we use the benchmark suites used by the original authors.…”

Section: Experimental Results and Evaluationmentioning

confidence: 99%

“…SIMPLER uses efficient compiler like register allocation technology to generate an optimized mapping for huge computations within seconds. Compared to previous work that optimizes latency rather than throughput for a single function ( [24], [25]), SIMPLER achieves an average throughput improvement of over 435× for a memory array with 512 rows. When the previous tools are parallelized in a similar manner to SIMPLER, SIMPLER offers at least 5× higher throughput and 23× smaller area usage.…”

Section: Introductionmentioning

confidence: 88%

“…Motivated by the computational burden of solving optimization problems, Yadav et al [24] suggested heuristics for finding a mapping. Instead of generating the mapping with the maximum number of aligned gates (thus, with maximum parallelism and minimum latency), the unaligned gate outputs required as inputs for other gates were moved by adding copy cycles.…”

Section: Related Workmentioning

confidence: 99%

“…Recent work has focused on automatic conversion of arbitrary logical functions to a sequence of executions within the memory. In [23], [24], tools were developed to generate execution sequences for arbitrary logical functions, while minimizing the computational latency in a memristive memory setup. Latency is minimized for a single computation instance by exploiting parallelism features of in-memory stateful logic operations so to execute several NOR operations within an instance in a single cycle.…”

Section: Introductionmentioning

confidence: 99%

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SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput

Ben-Hur

Ronen

Haj-Ali

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In-memory processing can dramatically improve the latency and energy consumption of computing systems by minimizing the data transfer between the memory and the processor. Efficient execution of processing operations within the memory is therefore a highly motivated objective in modern computer architecture. This paper presents a novel automatic framework for efficient implementation of arbitrary combinational logic functions within a memristive memory. Using tools from logic design, graph theory and compiler register allocation technology, we developed SIMPLER (Synthesis and In-memory MaPping of Logic Execution in a single Row), a tool that optimizes the execution of in-memory logic operations in terms of throughput and area. Given a logical function, SIMPLER automatically generates a sequence of atomic Memristor-Aided loGIC (MAGIC) NOR operations and efficiently locates them within a single size-limited memory row, reusing cells to save area when needed. This approach fully exploits the parallelism offered by the MAGIC NOR gates. It allows multiple instances of the logic function to be performed concurrently, each compressed into a single row of the memory. This virtue makes SIMPLER an attractive candidate for designing in-memory Single Instruction, Multiple Data (SIMD) operations. Compared to previous work (that optimizes latency rather than throughput for a single function), SIMPLER achieves an average throughput improvement of 435×. When previous tools are parallelized similarly to SIMPLER, SIMPLER achieves higher throughput of at least 5×, with 23× improvement in area and 20× improvement in area efficiency. These improvements more than fully compensate for the increase (up to 17% on average) in latency.

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Memristive Stateful Logic for Edge Boolean Computers

Kim

Son

Kim

2021

Advanced Intelligent Systems

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Memristive stateful logic enables complete in-memory computing, allowing low-power and low-cost Boolean computing. Its characteristics are consistent with the requirements of edge computing devices, which will occupy a considerable segment in the coming Internet of things (IoT) era. In this review, recent developments in stateful logic technology are intensively explored. The topics include a summary of the evolution of stateful logic gates and their cascading strategies for Boolean computing. Also, array-level data manipulation is discussed, and its role in realizing massive computation inside the memory. Finally, the logic operation error issue is discussed, with feasible solutions.

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Look-ahead mapping of Boolean functions in memristive crossbar array

Cited by 30 publications

References 17 publications

Memristive Logic in Crossbar Memory Arrays: Variability-Aware Design for Higher Reliability

Memristive Logic in Crossbar Memory Arrays: Variability-Aware Design for Higher Reliability

SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput

Memristive Stateful Logic for Edge Boolean Computers

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