Long-range stresses generated by misfit dislocations in epitaxial films

Trukhanov, E. M.; Колесников, А. В.; Loshkarev, I. D.

doi:10.1134/s1063739715080119

Cited by 30 publications

(25 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…One way to decrease dimensions of elements of integrated circuits is manufacturing them in thin film heterostructures [3][4][5]11]. In this case it is possible to use in homogeneity of heterostructure and necessary optimization of doping of electronic materials [12] and development of epitaxial technology to improve these materials (including analysis of mismatch induced stress) [13][14][15]. An alternative approaches to increase dimensions of integrated circuits are using of laser and microwave types of annealing [16][17][18].…”

Section: Introductionmentioning

confidence: 99%

On Optimization of Manufacturing of an Independent Current Source Based on Heterostructures to Increase Density of their Elements. Influence of Miss-Match Induced Stress

2020

International Journal of Innovative Research in Electronics and

View full text Add to dashboard Cite

In this paper we introduce an approach to increase density of field-effect transistors framework an independent current source. Framework the approach we consider manufacturing the inverter in heterostructure with specific configuration. Several required areas of the heterostructure should be doped by diffusion or ion implantation. After that dopant and radiation defects should by annealed framework optimized scheme. We also consider an approach to decrease value of mismatch-induced stress in the considered heterostructure. We introduce an analytical approach to analyze mass and heat transport in heterostructures during manufacturing of integrated circuits with account mismatch-induced stress.

show abstract

Section: Introductionmentioning

confidence: 99%

On Optimization of Manufacturing of an Independent Current Source Based on Heterostructures to Increase Density of their Elements. Influence of Miss-Match Induced Stress

2020

International Journal of Innovative Research in Electronics and

View full text Add to dashboard Cite

show abstract

“…One way to decrease dimensions of elements of integrated circuits is manufacturing them in thin film heterostructures [3][4][5]11]. In this case it is possible to use inhomogeneity of heterostructure and necessary optimization of doping of electronic materials [12] and development of epitaxial technology to improve these materials (including analysis of mismatch induced stress) [13][14][15]. An alternative approach to increase dimensions of integrated circuits are using of laser and microwave types of annealing [16][17][18].…”

Section: Introductionmentioning

confidence: 99%

An Approach to Manufacture Small Multiplexer with Dense Field-Effect Transistors

Pankratov¹

2019

EJEE

View full text Add to dashboard Cite

This paper introduces an approach to manufacture a small multiplexer with dense field-effect transistors. First, a framework of two-level current-mode logic gates was designed for the transistors. The logic gates are organized heterogeneously with a substrate, epitaxial layers and buffer layer. Considering the different properties of materials in the framework, the density of transistors was improved by annealing dopant and/or radiation defects, thus reducing the size of the multiplexer. In addition, the mismatch-induced stress was alleviated through ion implantation. Next, an analytical approach was developed to analyze the mass and heat transport in the heterogenous framework during the production of integrated circuits, in the presence of mismatch-induced stress. The proposed method makes it possible to capture both nonlinear variations of parameters in space and time through the production process.

show abstract

“…One way to decrease dimensions of elements of integrated circuits is manufacturing them in thin film heterostructures [3][4][5]11]. In this case it is possible to use inhomogeneity of heterostructure and necessary optimization of doping of electronic materials [12] and development of epitaxial technology to improve these materials (including analysis of mismatch induced stress) [13][14][15]. An alternative approaches to increase dimensions of integrated circuits are using of laser and microwave types of annealing [16][17][18].…”

Section: Introductionmentioning

confidence: 99%

Prognosis of Manufacturing of a Two-Level Current-Mode Logic Gate in Latch Based on Heterostructures to Increase Density of their Elements with Account Miss-Match Induced Stress and Porosity of Materials on Technological Process. On Approach for Optimization of Manufacturing

2019

International Journal of Innovative Research in Electronics and

View full text Add to dashboard Cite

In this paper we introduce an approach to increase density of field-effect transistors framework a two-level current-mode logic gate in latch. Framework the approach we consider manufacturing the logic gate in heterostructure with specific configuration. Several required areas of the heterostructure should be doped by diffusion or ion implantation. After that dopant and radiation defects should by annealed framework optimized scheme. We also consider an approach to decrease value of mismatch-induced stress in the considered heterostructure. We introduce an analytical approach to analyze mass and heat transport in heterostructures during manufacturing of integrated circuits with account mismatch-induced stress.

show abstract

Long-range stresses generated by misfit dislocations in epitaxial films

Cited by 30 publications

References 15 publications

On Optimization of Manufacturing of an Independent Current Source Based on Heterostructures to Increase Density of their Elements. Influence of Miss-Match Induced Stress

On Optimization of Manufacturing of an Independent Current Source Based on Heterostructures to Increase Density of their Elements. Influence of Miss-Match Induced Stress

An Approach to Manufacture Small Multiplexer with Dense Field-Effect Transistors

Prognosis of Manufacturing of a Two-Level Current-Mode Logic Gate in Latch Based on Heterostructures to Increase Density of their Elements with Account Miss-Match Induced Stress and Porosity of Materials on Technological Process. On Approach for Optimization of Manufacturing

Contact Info

Product

Resources

About