Logic Synthesis for RRAM-Based In-Memory Computing

Shirinzadeh, Saeideh; Soeken, Mathias; Gaillardon, Pierre-Emmanuel; Drechsler, Rolf

doi:10.1109/tcad.2017.2750064

Cited by 45 publications

(31 citation statements)

References 27 publications

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“…In [42][43][44], majority gate is implemented in RRAM array (1S-1R) by applying two inputs of the majority gate as voltages at W L and BL of the array (the third input being the initial state of the RRAM) and the output is the new non-volatile state of the device. Hence this way of implementing majority can be called V-R logic, though in the strict sense, it should be VandR-R logic since the third input is resistance (initial state of the RRAM).…”

Section: V-r Majority Logicmentioning

confidence: 99%

“…A comparison between V-R logic and R-V logic is presented pictorially in Figure 4. In the V-R implementation [42][43][44] in memory, the inputs of the majority gate are applied as voltages at W L/BL. This manner of computation complicates the row/column decoders of the memory array, which were conventionally used to select rows/columns.…”

Section: Kωmentioning

confidence: 99%

“…This will aid the implementation of in-memory parallel-prefix adders (Section 5) and ternary computing [47]. [45,46] (c) When multiple gates have to be executed in parallel, the majority gates of [42][43][44] have to be mapped diagonally because two gates cannot be executed in the same row/column.…”

Section: Kωmentioning

confidence: 99%

See 2 more Smart Citations

Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

Reuben

2020

JLPEA

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As we approach the end of Moore’s law, many alternative devices are being explored to satisfy the performance requirements of modern integrated circuits. At the same time, the movement of data between processing and memory units in contemporary computing systems (‘von Neumann bottleneck’ or ‘memory wall’) necessitates a paradigm shift in the way data is processed. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic which has been found to be an efficient logic primitive due to its expressive power. In this review, the efficiency of majority logic is analyzed from the perspective of in-memory computing. Recently reported methods to implement majority gate in Resistive RAM array are reviewed and compared. Conventional CMOS implementation accommodated heterogeneity of logic gates (NAND, NOR, XOR) while in-memory implementation usually accommodates homogeneity of gates (only IMPLY or only NAND or only MAJORITY). In view of this, memristive logic families which can implement MAJORITY gate and NOT (to make it functionally complete) are to be favored for in-memory computing. One-bit full adders implemented in memory array using different logic primitives are compared and the efficiency of majority-based implementation is underscored. To investigate if the efficiency of majority-based implementation extends to n-bit adders, eight-bit adders implemented in memory array using different logic primitives are compared. Parallel-prefix adders implemented in majority logic can reduce latency of in-memory adders by 50–70% when compared to IMPLY, NAND, NOR and other similar logic primitives.

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Section: V-r Majority Logicmentioning

confidence: 99%

Section: Kωmentioning

confidence: 99%

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Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

Reuben

2020

JLPEA

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“…One of the most promising approaches in this field is hybrid Nano/CMOS technology. This is due to the unique characteristics of Memristors such as being capable of scaling to Nano-metric sizes [5][6][7][8][9] and having a very fast response time [10].…”

Section: Introductionmentioning

confidence: 99%

“…A diversity of Memristor devices based on resistance switching property exist, which use different materials and algorithms [7][8][9]. The Memristors arrays are used in a variety of today's electronic circuits [10][11][12][13][14][15][16][17][18][19][20][21].…”

Section: Introductionmentioning

confidence: 99%

Novel design for Memristor‐based n to 1 multiplexer using new IMPLY logic approach

Karimi

Rezai

2019

IET Circuits, Devices & Systems

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Multiplexer is one of the widely used logics in VLSI design. This paper presents a novel method to design the n-input Memristor-based AND and OR operations. Then, two methods are proposed to design complete and incomplete n to 1 Memristor-based multiplexers (MUXs) based on these novel Memristor-based AND and OR operations. The simulation results confirm the accuracy and functionality of the proposed methods. The comparison between n to 1 MUXs shows that the proposed n to 1 MUXs provide improvements in terms of area and speed compared to other n to 1 MUXs.

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Memristive Stateful Logic for Edge Boolean Computers

Kim

Son

Kim

2021

Advanced Intelligent Systems

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Memristive stateful logic enables complete in-memory computing, allowing low-power and low-cost Boolean computing. Its characteristics are consistent with the requirements of edge computing devices, which will occupy a considerable segment in the coming Internet of things (IoT) era. In this review, recent developments in stateful logic technology are intensively explored. The topics include a summary of the evolution of stateful logic gates and their cascading strategies for Boolean computing. Also, array-level data manipulation is discussed, and its role in realizing massive computation inside the memory. Finally, the logic operation error issue is discussed, with feasible solutions.

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Logic Synthesis for RRAM-Based In-Memory Computing

Cited by 45 publications

References 27 publications

Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

Novel design for Memristor‐based n to 1 multiplexer using new IMPLY logic approach

Memristive Stateful Logic for Edge Boolean Computers

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