2020 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) 2020
DOI: 10.1109/ipfa49335.2020.9261000
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Logic State Imaging From FA Techniques for Special Applications to One of the Most Powerful Hardware Security Side-Channel Threats

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Cited by 7 publications
(4 citation statements)
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“…Our attack approach has already been sketched in [43] and assumes that the adversary has access to a training device, for which she can control the contained secret at her will. However, she does not have any knowledge about the design of the chip and the location of the key storage.…”
Section: Attack Approachmentioning
confidence: 99%
“…Our attack approach has already been sketched in [43] and assumes that the adversary has access to a training device, for which she can control the contained secret at her will. However, she does not have any knowledge about the design of the chip and the location of the key storage.…”
Section: Attack Approachmentioning
confidence: 99%
“…Recently, EOFM has also been treated as a new class of physical attack that is fast becoming a key instrument in the hardware security community [5,6]. Without making any physical contact with ICs, an adversary can probe volatile and on-die-only secret data from the backside of a chip just with the help of an EOFM technique [7][8][9][10]. However, the physical mechanisms of EOFM signals from modern ICs have not been understood completely to date.…”
Section: Introductionmentioning
confidence: 99%
“…However, they remain jeopardized by the evolution of front-side and back-side invasive and semiinvasive attacks [1], [2], [3], [4]. Many physical inspection methods such as focused ion beam (FIB) micro-probing, FIB circuit editing, and contact-less optical probing, for failure analysis and defect localization [5], [6] have been utilized to identify regions of interests and/or extract sensitive information. SEM-based imaging, in combination with iterative integrated circuit (IC) deprocessing, can be used to recover the layout and eventually the gate-level netlist of a semiconductor IP [7], [8].…”
Section: Introductionmentioning
confidence: 99%