Logic Shrinkage

Abstract

FPGA-specific DNN architectures using the native LUTs as independently trainable inference operators have been shown to achieve favorable area-accuracy and energy-accuracy tradeoffs. The first work in this area, LUTNet, exhibited state-of-the-art performance for standard DNN benchmarks. In this paper, we propose the learned optimization of such LUT-based topologies, resulting in higher-efficiency designs than via the direct use of off-the-shelf, hand-designed networks. Existing implementations of this class of architecture require the manual specification of the number of inputs per LUT, 𝐾. Choosing appropriate 𝐾 a priori is challenging, and doing so at even high granularity, e.g. per layer, is a time-consuming and error-prone process that leaves FPGAs' spatial flexibility underexploited. Furthermore, prior works see LUT inputs connected randomly, which does not guarantee a good choice of network topology. To address these issues, we propose logic shrinkage, a fine-grained netlist pruning methodology enabling 𝐾 to be automatically learned for every LUT in a neural network targeted for FPGA inference. By removing LUT inputs determined to be of low importance, our method increases the efficiency of the resultant accelerators. Our GPU-friendly solution to LUT input removal is capable of processing large topologies during their training with negligible slowdown. With logic shrinkage, we better the area and energy efficiency of the best-performing LUTNet implementation of the CNV network classifying CIFAR-10 by 1.54× and 1.31×, respectively, while matching its accuracy. This implementation also reaches 2.71× the area efficiency of an equally accurate, heavily pruned BNN. On ImageNet with the Bi-Real Net architecture, employment of logic shrinkage results in a post-synthesis area reduction of 2.67× vs LUTNet, allowing for implementation that was previously impossible on today's largest FPGAs.

Table-Lookup MAC: Scalable Processing of Quantised Neural Networks in FPGA Soft Logic

“…Previous works on soft-logic computing frequently lack the scalability to support the model sizes necessary for ImageNet classification [2,28]. Among the existing solutions, only LUTNet [30] and Logic Shrinkage [31] have reported results on this dataset, albeit with certain constraints.…”

“…Binary Neural Network (1b) [30,31] customises and constrains the training process to achieve LUT compatibility, TLMAC derives optimised LUT initialisations from state-of-the-art quantised models directly. function as both a compute engine and traditional memory [3,7,32].…”

“…In LUTNet [30], pruning was applied and simple XNOR operations were transformed into Boolean functions with more inputs and higher complexity, significantly increasing the logic density. Logic Shrinkage [31] took this further by eliminating LUTs of low importance. Despite these optimisations, however, scalability remains an issue and FPGA resources were only sufficient to accommodate a single AlexNet layer or ResNet block, respectively.…”

“…Prior Works. To put the capabilities of the TLMAC hardware architecture and compilation algorithms into 7: Area-accuracy trade-off for TLMAC and previous works LUTNet [30] and LogicShrinkage [31]. TLMAC shifts the Pareto frontier further inward as lower error can be achieved with significantly smaller area.…”

FlightLLM: Efficient Large Language Model Inference with a Complete Mapping Flow on FPGAs

“…FPGAs are potential solutions to accelerate LLM inference and explore the benefits brought by model compression, which has been proven in previous deep learning models [21,22,39,43,55]. However, efficient LLM inference on FPGAs needs to solve the following challenges (Fig.…”