1988
DOI: 10.1137/0217042
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Locality, Communication, and Interconnect Length in Multicomputers

Abstract: We derive a lower bound on the average interconnect (edge) length in d-dimensional embeddings of arbitrary graphs, expressed in terms of diameter and symmetry. It is optimal for all graph topologies we have examined, including complete graph, star, binary n-cube, cube-connected cycles, complete binary tree, and mesh with wraparound (e.g., torus, ring). The lower bound is technology independent, and shows that many interconnection topologies of today's multicomputers do not scale well in the physical world (d 3… Show more

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Cited by 68 publications
(27 citation statements)
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“…The results are only speculative because of a 1 We use whp, with high probability to mean with probability at least § ¥ © § ! [14,15]. The length of wires between routing nodes increases with respect to the physical space required.…”
Section: Analysis Of Systolic Routingmentioning
confidence: 99%
“…The results are only speculative because of a 1 We use whp, with high probability to mean with probability at least § ¥ © § ! [14,15]. The length of wires between routing nodes increases with respect to the physical space required.…”
Section: Analysis Of Systolic Routingmentioning
confidence: 99%
“…As the number of processors and memory blocks gets into the thousands, making all the high-speed connections becomes costly. To address the objection that wires are thin, Vitányi treated wires as having no volume in showing that exponential computations cannot be completed in polynomial time with parallelism [22]. In our case if wires are assumed to have zero thickness but non-zero cost per unit length, the wiring costs in Section 2.1 drop from Θ(n 3/2 ) to Θ(n 4/3 ), the number of components in Theorem 1 drops to Θ(p + m + pr(p + m) 1/3 ), the full cost in Corollary 1 drops to Θ((T /p)(p + m + pr(p + m) 1/3 )), and Corollary 2 is unaffected.…”
Section: Objectionsmentioning
confidence: 99%
“…Whereas an optimized network with small diameter and large bisection width is desirable, its cost/performance ratio suffers from dramatically increased area and wire length [6], [32]. For optimal PRC rings, this leads to the layout area yx P alog P x and the length of the longest wire yxalogx, which are of the same orders of magnitude as the respective requirements of CCC networks [28].…”
Section: Vlsi Layout and Scalabilitymentioning
confidence: 99%