Lneuro 1.0: a piece of hardware LEGO for building neural network systems

Mauduit, Nicolas; Duranton, Marc; Gobert, Jean; Sirat, J. A.

doi:10.1109/72.129414

Cited by 61 publications

(13 citation statements)

References 20 publications

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“…The performance is also expected to be comparable or superior to most other NN-dedicated systems (e.g., the RAP, 102 MCUPS on the back-propagation problem [16]) or VLSI accelerators (Lneuro 1.0, 32 MCUPS [17]). The CNAPS Server 11/512 [11] has a higher peak performance of 1,950 MCUPS (at a lower precision) thanks to a higher clock rate, parallel PE communication, and a far more advanced VLSI technology.…”

Section: Performancementioning

confidence: 92%

GENES IV: A bit-serial processing element for a multi-model neural-network accelerator

Ienne

Viredaz

1995

Journal of VLSI Signal Processing

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Abstract.A systolic array of dedicated processing elements (PEs) is presented as the heart of a multi-model neural-network accelerator. The instruction set of the PEs makes possible to implement several widely-used neural models, including multi-layer Perceptrons with the back-propagation learning rule and Kohonen feature maps. Each PE holds an element of the synaptic weight matrix. An instantaneous swapping mechanism for the weight matrix makes the efficient implementation of neural networks larger than the physical PE array possible. A systolicallyflowing instruction accompanies each input vector propagating in the array. This avoids the need of emptying and refilling the array when the operating mode of the array is changed. Fixed point arithmetic is used in the PE. The problem of optimally scaling real variables in fixed-point format is addressed.Both the GENES IV chip, containing a matrix of 2 • 2 PEs, and an auxiliary arithmetic circuit have been manufactured and successfully tested. The MANTRA I machine has been built around these chips. Peak performances of the full system are between 200 and 400 MCPS in the evaluation phase and between 100 and 200 MCUPS during the learning phase (depending on the algorithm being implemented).

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Section: Performancementioning

confidence: 92%

GENES IV: A bit-serial processing element for a multi-model neural-network accelerator

Ienne

Viredaz

1995

Journal of VLSI Signal Processing

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“…Let us call this top-down pattern . The resulting vector X is given by the equation, (6) Since only one y j is active, let us call this winning F2 node y J , so that y j =0 if and y J =1. In this case we can state (7) where .…”

Section: A Vlsi-friendly Art1 Algorithmmentioning

confidence: 99%

A real-time clustering microchip neural engine

Serrano-Gotarredona

Linares-Barranco

1996

IEEE Trans. VLSI Syst.

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This paper presents an analog current-mode VLSI implementation of an unsupervised clustering algorithm. The clustering algorithm is based on the popular ART1 algorithm [1], but has been modified resulting in a more VLSI-friendly algorithm [2], [3] that allows a more efficient hardware implementation with simple circuit operators, little memory requirements, modular chip assembly capability, and higher speed figures. The chip described in this paper implements a network that can cluster 100 binary pixels input patterns into up to 18 different categories. Modular expansibility of the system is directly possible by assembling an N×M array of chips without any extra interfacing circuitry, so that the maximum number of clusters is 18×M and the maximum number of bits of the input pattern is N×100. Pattern classification and learning is performed in 1.8µs, which is an equivalent computing power of 4.4×10 9 connections per second plus connection-updates per second. The chip has been fabricated in a standard low cost 1.6µm double-metal single-poly CMOS process, has a die area of 1cm 2 , and is mounted in a 120-pin PGA package. Although internally the chip is analog in nature, it interfaces to the outside world through digital signals, and thus has a true asynchronous digital behavior. Experimental chip test results are available, obtained through digital chip test equipment. Fault tolerance at the system level operation is demonstrated through the experimental testing of faulty chips.

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“…Commercial coprocessor boards consist of floating point or signal processing accelerator boards with large amounts of memory. Some examples are: (i) CONE [4,45], (ii) NNETS [38], (iii) NETSIM [38], (iv) RAP [34], (v) Lneuro 1.0 [33], (vi) neuroTRAM [10], (vii) HERCULES [23], (viii) Kotilainen [35], (ix) the WAP [26], and (iix) Spert [21]. There have been several commercial neural network chips developed in the industry.…”

Section: Introductionmentioning

confidence: 99%