LMS based adaptive bit weights error extraction algorithm used in high resolution A/D converters

Li, Ting; Wang, Yuxin; Zhang, Yong; Huang, Zhengbo

doi:10.1109/inec.2016.7589289

Cited by 1 publication

(2 citation statements)

References 3 publications

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“…Comparing to the prior works [1,3,4], this method costs the fewest convergence time and gets the best correction results. The calibration converges within 4K sampling, which is only 4% of [1], 15% of that [3] and 6.25% of that [4]. This performance shows that this design has an obvious advantage for ultra-high-resolution SAR ADC to implement.…”

Section: Discussionmentioning

confidence: 97%

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Rapid calibration of bits weights error for high‐resolution successive approximation register ADC

Liu

Xu²,

2019

IET Circuits, Devices & Systems

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This study presents the rapid calibration of bits weights error for an 18 bit successive approximation register analogue-to-digital converter (ADC). This calibration technique is a new hybrid algorithm. Comparing to the traditional methods, this technique significantly reduces the convergence time and improves the accuracy of bits weights error estimation. There is no wasteful time in the correction process. This proposed approach estimates the bits weights error not only from the digital-toanalogue converter capacitor mismatch, inter-stage gain error, but also the metal insulator metal (MIM), capacitor second-order voltage coefficient in the ultra-high-resolution ADC. The proposed algorithm has been verified with a test 18 bit ADC chip, where measured results show the calibration is able to improve the peak integral nonlinearity (INL), of the ADC from 29 to 1.0 LSB after calibration. Measured results also show the signal-to-noise and distortion ratio/spurious-free dynamic range of the ADC improves from 83/94 to 96/127 dB after calibration. It will be seen that the calibration is achieved in ∼4k cycles, which is more than ×25 faster than previously published algorithm.

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Section: Discussionmentioning

confidence: 97%

“…However, the capacitance array mismatch and MIM capacitor second-order voltage coefficient contribute bits weights errors, which worsened the SAR ADC linearity performance. Thereby the calibration of high-resolution SAR ADC is absolutely necessary [1][2][3][4][5][6][7][8][9][10].…”

Section: Introductionmentioning

confidence: 99%

Rapid calibration of bits weights error for high‐resolution successive approximation register ADC

Liu

Xu²,

2019

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

show abstract

LMS based adaptive bit weights error extraction algorithm used in high resolution A/D converters

Cited by 1 publication

References 3 publications

Rapid calibration of bits weights error for high‐resolution successive approximation register ADC

Rapid calibration of bits weights error for high‐resolution successive approximation register ADC

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