Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems

Höppner, Sebastian; Yan, Yexin; Vogginger, Bernhard; Dixius, Andreas; Partzsch, Johannes; Joshi, Prateek; Neumärker, Felix; Hartmann, Stephan; Schiefer, Stefan; Scholze, Stefan; Ellguth, Georg; Cederstroem, Love; Eberlein, Matthias; Mayr, Christian; Temple, Steve; Plana, Luis A.; Garside, Jim; Davison, Simon; Lester, David; Furber, Steve

doi:10.1109/iscas.2017.8050396

Cited by 3 publications

(2 citation statements)

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“…10, consisting of a power supply PCB hosting up to 4 chip modules and an FPGA board for host PC communication over Ethernet. A graphical user interface running on the host PC allows exploration of the DVFS measurements [32]. The achieved performance at PL1 and PL2 has been analyzed from sign-off timing analyses.…”

Section: Test Chipmentioning

confidence: 99%

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Dynamic Power Management for Neuromorphic Many-Core Systems

Hoeppner¹,

Vogginger²,

Yan³

et al. 2019

Preprint

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This work presents a dynamic power management architecture for neuromorphic many core systems such as SpiN-Naker. A fast dynamic voltage and frequency scaling (DVFS) technique is presented which allows the processing elements (PE) to change their supply voltage and clock frequency individually and autonomously within less than 100 ns. This is employed by the neuromorphic simulation software flow, which defines the performance level (PL) of the PE based on the actual workload within each simulation cycle. A test chip in 28 nm SLP CMOS technology has been implemented. It includes 4 PEs which can be scaled from 0.7 V to 1.0 V with frequencies from 125 MHz to 500 MHz at three distinct PLs. By measurement of three neuromorphic benchmarks it is shown that the total PE power consumption can be reduced by 75 %, with 80 % baseline power reduction and a 50 % reduction of energy per neuron and synapse computation, all while maintaining temporary peak system performance to achieve biological real-time operation of the system. A numerical model of this power management model is derived which allows DVFS architecture exploration for neuromorphics. The proposed technique is to be used for the second generation SpiNNaker neuromorphic many core system.

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Section: Test Chipmentioning

confidence: 99%

“…Fig.10. Measurement setup, PCB with power supply and up to 4 test chip modules, FPGA board and host PC GUI[32] …”

mentioning

confidence: 99%