2015
DOI: 10.1117/12.2086525
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Lithography overlay control improvement using patterned wafer geometry for sub-22nm technology nodes

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Cited by 4 publications
(2 citation statements)
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“…The resolution, overlay, and throughput are the three critical indicators of photolithography equipment [1,2]. The overlay error beyond the limitation may cause gross deviation of the IC components and devices, and lead to short circuits, open circuits and other problems [3][4][5]. According to the International Technology Roadmap for Semiconductors (ITRS) and other institutes, for process nodes of 10 nm and 7 nm, the overlay accuracy is required to be below 3 nm and 2 nm [6][7][8][9][10].…”
Section: Introductionmentioning
confidence: 99%
“…The resolution, overlay, and throughput are the three critical indicators of photolithography equipment [1,2]. The overlay error beyond the limitation may cause gross deviation of the IC components and devices, and lead to short circuits, open circuits and other problems [3][4][5]. According to the International Technology Roadmap for Semiconductors (ITRS) and other institutes, for process nodes of 10 nm and 7 nm, the overlay accuracy is required to be below 3 nm and 2 nm [6][7][8][9][10].…”
Section: Introductionmentioning
confidence: 99%
“…The overlay confined to a reasonable range would not lead to serious consequences. However, the error beyond the limitation may cause vital deviation of the components and devices from theoretical designed structures, which would result in short circuit, open circuit and other types of faults 6,7 . Generally the acceptable maximum value of overlay is 1/3 of the critical dimension (CD) 8 .…”
Section: Introductionmentioning
confidence: 99%