Link-Time Path-Sensitive Memory Redundancy Elimination

Abstract

Optimizations performed at link-time or directly applied to final program executables have received increased attention in recent years. This paper discusses the discovery and elimination of redundant memory operations in the context of a link-time optimizer, an optimization that we call Memory Redundancy Elimination (MRE). Previous research showed that existing MRE techniques are mainly based on path-insensitive information, which causes many MRE opportunities to be lost. We present a new technique for eliminating redundant loads in a path-sensitive fashion, by using a novel alias analysis algorithm that is able to expose path-sensitive memory redundancies. The paper also extends our previous work by removing both redundant and dead stores. Our experiments show that around 75% of load and 10% of store references in a program can be considered redundant, because they are accessing memory locations that have been referenced less than 256 memory instructions away. By combining our previous optimizations for eliminating load redundancies with the new techniques developed in this paper, we show that around 18% of the loads and 8% of the stores can be detected and eliminated, which translates into a 10% reduction in execution time.

A lifetime optimal algorithm for speculative PRE

“…Finally, we want to stress that PRE techniques are applicable to other areas of optimization such as load/store elimination by combining both control and data speculation [Lin et al 2003], load/store elimination for binaries [Fernández and Espasa 2004], communication optimization [Knoop and Mehofer 2002], and thread-level synchronization cost elimination [Zhai et al 2002]. Significant performance gains can be expected from these optimizations, leveraging the benefits of a more application-specific PRE technique that may be derived from our algorithm.…”

Binary Redundancy Elimination

“…From the above contributions and the work presented in this dissertation, we have produced several technical reports [FED01a,FE02a,FE03,FE04a] and publications [FED01b,FE02b,FED03,FE04c,FE04b].…”