Linearization of monolithic LNAs using low-frequency low-impedance input termination

Aparin, V.; Larson, L.E.

doi:10.1109/esscirc.2003.1257091

Cited by 41 publications

(34 citation statements)

References 5 publications

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“…As was shown in [2], the linearity of an Si bipolar junction transistor (BJT) or an SiGe HBT can be reliably improved using a simple technique based on low-frequency low-impedance base termination without degrading gain or NF. However, this technique is not effective for linearizing field-effect transistor (FET) amplifiers.…”

Section: Introductionmentioning

confidence: 99%

Modified derivative superposition method for linearizing FET low noise amplifiers

Aparin¹,

Larson²

2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers

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Section: Introductionmentioning

confidence: 99%

Modified derivative superposition method for linearizing FET low noise amplifiers

Aparin¹,

Larson²

2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers

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“…The tradeoff between linearity and power consumption has to be considered for lowpower handheld applications [1]. In addition, technology scaling causes linearity degradation because of lower supply voltage and high-field mobility effects [3].…”

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“…In addition, technology scaling causes linearity degradation because of lower supply voltage and high-field mobility effects [3]. On the other hand, noise constraints in multi-standard applications force designers to use active mixers which are vulnerable to large input signals because of exploiting input trans-conductance [1]. Therefore linearization techniques such as low-impedance termination, feed-forward, feedback, piece wise approximation and pre-post distortion have been proposed.…”

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confidence: 99%

“…By utilizing on-chip LC resonators and filtering signals at dc and two times of RF frequency, the second-order distortion component is eliminated at the input so the IM3 is reduced [1,7,18]. The technique is simple and works well but the on chip LC resonator consumes large chip area.…”

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confidence: 99%

“…The IM3 cancelation path converts the input signal to an output current so that the generated third-order derivatives have the same amplitude and opposite phase. Summing the output currents suppresses the IM3 while the fundamental tones are attenuated [1,5,14,16,20,21]. In this technique the IM3 suppression is sensitive to device characteristics and depends on the biasing voltages.…”

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High IIP3 and Low-Noise CMOS Mixer Using Non-linear Feedback Technique

Amirabadi

Chehelcheraghi

Kamarei

2011

Circuits Syst Signal Process

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A third-order intermodulation cancelation technique using a non-linear feedback is proposed to design a low-power low-distortion mixer in a 65 nm standard CMOS technology. The IM3 cancelation is achieved by estimating distorting error at a non-linear feedback element and subtracting it from the input. The linearization technique is utilized in the input trans-conductance of the mixer. The circuit functionality is analyzed using Volterra series. The covering frequency range of the mixer is 800 MHz to 5 GHz. The technique increases the input-referred third-order intercept point (IIP3) and input 1 dB compression point to +16.4 dBm and −1.87 dBm, respectively. It obtains a gain of 9 dB and an input-referred noise of 1.84 nV/ √ Hz while consumes 8.75 mA from 1.2 V supply. The layout of the mixer occupies 0.315 mm × 0.296 mm of silicon area.

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Reconfigurable RF Power Amplifiers on Silicon for Wireless Handsets

Leyssenne¹,

Kerherv²,

Deval³

2011

Analog Circuits and Signal Processing

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No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work.Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com) PrefaceThe design of power amplifiers (PA) for wireless applications has been a topic of great concern among the scientific community in electronics since the early 1990s. Power amplifiers dominantly determine the power efficiency and battery lifetime of modern mobile terminals. PA linearity is a key feature that limits the maximum allowed data rate of a radio link. The deployment of always more complex radio networks with a continuously growing throughput sharpens the specifications of power amplifiers. The market of wireless handsets (cellular phones, . . .) pushes manufacturers towards multi-standard capabilities (3G, Bluetooth, WIFI) and a growing level of integration. The Bill-of-Material and the consumed die area that are affordable are constantly reduced for cost purpose. The trade-offs that are inherent to PA design are therefore extremely stringent and no technical/technological solution can unanimously be regarded as a definitive contribution. To this date, the market of handset-dedicated power amplifiers is widely dominated by III/V technologies. However, throughout the following pages, we will try to highlight the benefits of PA integration on silicon. The architectures that will be proposed hereunder take advantage of silicon capabilities and strength, among others their relatively low cost and their ability to combine high power devices with low-power analog/digital control circuitry.Chapter 1 will first present the respective features of 2nd and 3rd generation cellular applications (GSM, DCS, EDGE, WCDMA. . .) and data transmission standards (WIFI, WIMAX, LTE). An overview of the most commonly employed RF power amplifier topologies will also be provided, with their advantages and drawbacks. Finally, the 0.25 µm BICMOS ST Microelectronics technology will be described and compared with III/V processes in the prospect of PA development. The fundamental features of power devices will be detailed and the most appropriate technological choice prior to the PA design itself will be discussed.In Chapters 2 and 3, several novel PA topologies will be proposed and discussed in terms of efficiency, linearity and complexity by means of mixed system/transistorlevel analyses. Chapter 2 will investigate three novel switched-mode power amplifier topologies. The first non-constant-gain principle is based on the power stage bypass/extinction and applied to a silicon HBT demonstrator. A silicon HBT demonstrator that was developed in the frame of RNRT ASTURIES project will be v vi Preface presented The other two topologies...

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Linearization of monolithic LNAs using low-frequency low-impedance input termination

Cited by 41 publications

References 5 publications

Modified derivative superposition method for linearizing FET low noise amplifiers

Modified derivative superposition method for linearizing FET low noise amplifiers

High IIP3 and Low-Noise CMOS Mixer Using Non-linear Feedback Technique

Reconfigurable RF Power Amplifiers on Silicon for Wireless Handsets

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