Linearity Performance Analysis Due to Lateral Straggle Variation in Hetero-Stacked TFET

Vanlalawmpuia, K.; Bhowmick, Brinda

doi:10.1007/s12633-019-00189-3

Cited by 18 publications

(7 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This enhancement in the values of I ON , I OFF , the I ON /I OFF ratio, V th and SS has already been reported in our earlier work [25]. Further, these performance parameters such as I ON , I OFF , I ON /I OFF , V th and SS of the stated device are also compared with related values for TFETs reported in the literature [22,23,[36][37][38][39] and tabulated in table 1. For the HMSDG-TFET reported in the current study, device simulation revealed a I ON of 2.5 × 10 -4 A µm −1 , which is higher compared with a CP-Ring TFET [22], ED-TFET [23], DM-DG-VTEFT [36], EDTFET [37], LWS-TFET and LWLS-TFET [38] and HS-TFET [39] as reported in the literature.…”

Section: Parameters Present Worksupporting

confidence: 73%

“…Gupta et al [22] Kondekar et al [23] Paras et al [36] Venkatesh et al [37] Yadav et al [38] Vanlalawmpuia et al [39] I ON (A µm −1 Gupta et al [22] Charge plasma-based ring-TFET (CP-Ring TFET)…”

Section: Parameters Present Workmentioning

confidence: 99%

“…Yadav et al [38] Low work-function strip (LWS) electrically doped TFET and low work-function live strip (LWLS) electrically doped TFET Vanlalawmpuia et al [39] Hetero-stacked TFET (HS-TFET) et al [35]. With application of a positive V gs , a narrow tunneling window formed at the source-channel junction, attributed to an increase in BTBT rate which in turn increases I ON .…”

Section: Parameters Present Workmentioning

confidence: 99%

See 2 more Smart Citations

A novel source material engineered double gate tunnel field effect transistor for radio frequency integrated circuit applications

Dassi

Madan

Pandey

et al. 2020

Semicond. Sci. Technol.

View full text Add to dashboard Cite

Tunnel field effect transistors (TFETs) have proved their potential for many possible electronic circuit applications. However, with the variety of TFET structures being worked upon it has been an unresolved challenge to optimize them for the applications to which they are best suited. In this paper we present a detailed comparative analysis of the linearity distortion and the radiofrequency (RF) performance parameters of a proposed heterojunction Mg2Si source double gate TFET (HMSDG-TFET) and a conventional homojunction Si source DG-TFET (SSDG-TFET). A source material engineering scheme is utilized to implement a staggered type 2 heterojunction at the source–channel junction by replacing the source material with Mg2Si (a low band gap material) to enhance the ON current (2.5 × 10–4 A µm−1), reduce the threshold voltage (0.26 V) and achieve a steeper subthreshold swing (10.05 mV decade−1). For linearity and distortion analysis, the figure of merit (FOM)-like higher-order transconductances, second- and third-order voltage intercepts, third-order intercept point, third-order intermodulation distortion, zero crossover point, 1 dB compression point, second-order harmonic distortion, third order harmonic distortion and total harmonic distortion have been examined. To portray the possible application of devices under consideration for RF integrated circuit applications, both structures are investigated for RF FOMs such as power gains, cutoff frequency (fT), maximum oscillation frequency (F max) and admittance parameters. Investigations carried out using a Silvaco ATLAS device simulator tool revealed that with fT approximately three orders higher (0.49 THz) and F max approximately two orders higher (0.9 THz) than that of a SSDG-TFET, the HMSDG-TFET is an appropriate candidate for use in high-frequency, high-linearity, low-distortion and low-power analog/RF applications.

show abstract

Section: Parameters Present Worksupporting

confidence: 73%

Section: Parameters Present Workmentioning

confidence: 99%

Section: Parameters Present Workmentioning

confidence: 99%

See 1 more Smart Citation

A novel source material engineered double gate tunnel field effect transistor for radio frequency integrated circuit applications

Dassi

Madan

Pandey

et al. 2020

Semicond. Sci. Technol.

View full text Add to dashboard Cite

show abstract

“…Short channel effects (SCEs) and an increase in leakage current are the main issues with downscaling the CMOS technology node [1][2][3][4]. Moreover, at room temperature T=300K, the scalability of threshold voltage V T is also limited due to Boltzmann tyranny (SS ≡ KT q .ln 10 ≈ 60 mV/decade) that decides the steepest nature of the transition between on and off state [5][6][7][8][9].…”

Section: Introductionmentioning

confidence: 99%

Simulation-Based Analysis of Ultra Thin-Body Double Gate Ferroelectric TFET for an Enhanced Electric Performance

Gopal

Varma

2021

Silicon

View full text Add to dashboard Cite

The Ultrathin body double gate FE layer TFET(UTB-DG-FE-TFET) is proposed and investigated in this work. Electrical performance parameters such as surface potential ψ(x), electrical field, drain current, sub-threshold swing, threshold voltage, and I on /I of f ratio are further analyzed using simulation-based analysis. Integration of Si: HF O 2 ferroelectric layer on top and bottom surfaces make the structure that provides negative capacitance, higher on current, enormous surface potential, peak electric field, and improvement in SS with degradation in off Current. The suggested design is evaluated in comparison with FE-TFET and standard TFET structures. Finally, the impact of device geometry variants like ferroelectric layer thickness (t f e ), intrinsic channel thickness t si , interfacial layer types, interfacial layer thickness (t ox ) and channel length Lc on transfer characteristics are investigated through 2D TCAD Sentaurus Simulator for a clear validation of its optimization. The recommended work demonstrates that it is a suitable device enabling superior performance and helpful in ultra-low-power applications.

show abstract

“…A comparative analysis of DC performance in terms of energy band diagram (EBD), transfer characteristics, electric field, electric potential, and analog/RF performance in terms of transconductance (g m1 ), gate-to-drain capacitance (C gd ), cut-off frequency (f T ), gainbandwidth product (GBP), and device efficiency (DE). Additionally, a device must maintain linearity, so that, nonlinear fragments at the output do not interfere with the desired signal [20,21]. So, the performance parameters such as g m2 , g m3 , VIP 2 , VIP 3 , IIP 3 , and third-order intermodulation distortion (IMD 3 ), evaluate the variation in device linearity characteristics due to interfering unwanted noise signals with different frequency components and maintain minimal or negligible higher-order harmonics and IMD at the output [22].…”

Section: Introductionmentioning

confidence: 99%

Interface trap charges associated reliability analysis of Si/Ge heterojunction dopingless TFET

Sharma

Basu

Kaur

2021

IET Circuits, Devices & Syst

View full text Add to dashboard Cite

The interface trap charges (ITC) associated reliability analysis of a charge-plasma based asymmetric double-gate (ADG) dopingless tunnel field effect transistor (DLTFET) with Si/Ge heterojunction and high-κ gate dielectric (HJADGDLTFET) has been studied. The HJADGDLTFET uses silicon at the drain and the channel region, and germanium at the source region, which enhances the band-to-band tunnelling at the source-channel junction, and hence drive current is increased by one order concerning ADGDLTFET. Also, ADG and high-κ dielectric (HfO 2 ) have been used to maintain low off-state current values. The primary intention of this work is to investigate the impact of ITC for HJADGDLTFET and compare it for ADGDLTFET considering DC, analog/RF, and linearity parameters such as transfer characteristics, electric-field, electric potential, first-, second-, and third-order transconductances (g m1 , g m2 , and g m3 ), gate-to-drain capacitance (C gd ), cut-off frequency (f T ), gain-bandwidth product, device efficiency, second-and third-order voltage intercept points (VIP 2 , VIP 3 ), third-order input intercept points (IIP 3 ), and third-order intermodulation distortion. The ATLAS simulation results show that the HJADGDLTFET is more immune to ITC variation than conventional ADGDLTFET concerning different polarities of ITC available at the semiconductoroxide interface.This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

show abstract

Linearity Performance Analysis Due to Lateral Straggle Variation in Hetero-Stacked TFET

Cited by 18 publications

References 23 publications

A novel source material engineered double gate tunnel field effect transistor for radio frequency integrated circuit applications

A novel source material engineered double gate tunnel field effect transistor for radio frequency integrated circuit applications

Simulation-Based Analysis of Ultra Thin-Body Double Gate Ferroelectric TFET for an Enhanced Electric Performance

Interface trap charges associated reliability analysis of Si/Ge heterojunction dopingless TFET

Contact Info

Product

Resources

About