Linear timing analysis of SOC synchronous circuits with level-sensitive latches

Taşkın, Barış; Kourtev, Ivan S.

doi:10.1109/asic.2002.1158085

Cited by 6 publications

(12 citation statements)

References 5 publications

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“…These are the latching, synchronization and propagation constraints [8]. Latching constraints bound the arrival time of the data signal X f (see Figure 1) to be latched into the final latch R f of a local data path.…”

Section: Clock Phasesmentioning

confidence: 99%

“…The MBM method (Table 2) is a collection of linearization procedures which replaces a non-linear constraint by a set of linear constraints, then adds a cost figure to the objective function [8]. The finite set N of variables {a, b, c,... ,n } satisfy N ⊂ ℜ, where ℜ is the real numbers set.…”

Section: Problem Formulationmentioning

confidence: 99%

“…The effects of time borrowing on circuit operation have been studied and are known to introduce non-linearity in the timing analysis of level-sensitive circuits [1, 2, 6,7,8,9]. The clock skew scheduling problem of edge-triggered (flip-flop-based) circuits has been broadly addressed in [4].…”

Section: Introductionmentioning

confidence: 99%

“…The clock skew scheduling problem of edge-triggered (flip-flop-based) circuits has been broadly addressed in [4]. The application of clock skew scheduling on level-sensitive circuits is addressed in [8] for a single-phase clocking scheme. Similar to the simultaneous consideration of time borrowing and clock skew scheduling, consideration of a multi-phase clocking scheme permits level-sensitive circuits to operate at higher operating frequencies.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Advanced timing of level-sensitive sequential circuits

Taşkın

Kourtev

Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004.

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This paper addresses the advanced timing analysis of multi-phase level-sensitive synchronous circuits under clock skew scheduling [4]. The timing analysis framework previously offered for a singlephase clocking scheme [8] is enhanced to accommodate a multiphase clocking scheme. In particular, the timing analysis framework is used to formulate the clock period minimization problem of multi-phase level-sensitive circuits. The modified big M method [8] is used to linearize the formulation of the clock period minimization problem and experiments are performed on the ISCAS'89 benchmark circuits. In single-phase level-sensitive circuits, up to 63% improvements over conventional zero clock skew, edge-triggered circuits are achieved through the simultaneous application of non-zero clock skew scheduling and time borrowing. Comparable improvements up to 62% are achieved for the same circuit topologies under a multi-phase clocking scheme.

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Section: Clock Phasesmentioning

confidence: 99%

Section: Problem Formulationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Advanced timing of level-sensitive sequential circuits

Taşkın

Kourtev

Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004.

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“…The increased complexity of the timing analysis, however, discourages use of such improved circuits in a typical design flow. Several timing analysis algorithms for circuits with varying topologies and clocking methodologies have been offered [1][2][3][4][5][6]. These algorithms are targeted to lower the solution complexities in order to increase the utilization of such alternate synchronous designs.…”

Section: Introductionmentioning

confidence: 99%

Time borrowing and clock skew scheduling effects on multi-phase level-sensitive circuits

Taşkın

Kourtev

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

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This paper addresses the effects of time borrowing and clock skew scheduling [1] on level-sensitive synchronous circuits. Synchronization of level-sensitive circuits can be accomplished through single-phase or multi-phase clocking schemes. This paper expands previous single-phase clock signal analysis [2] to include multiphase clock signal synchronization. The tradeoffs of synchronous circuit operation with different types of registers and synchronization schemes are analyzed. The presented timing analysis problem specifically targets clock period minimization. The modified big M method [2] is used to linearize the formulation of the timing analysis problem and experiments are performed on the ISCAS'89 benchmark circuits. For single and multi-phase level-sensitive circuits, up to 63% and 62% improvements, respectively, over conventional zero-skew, flip-flop based circuits are achieved through the simultaneous application of both time borrowing and non-zero clock skew scheduling.

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Timing Optimization Through Clock Skew Scheduling

2009

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Linear timing analysis of SOC synchronous circuits with level-sensitive latches

Cited by 6 publications

References 5 publications

Advanced timing of level-sensitive sequential circuits

Advanced timing of level-sensitive sequential circuits

Time borrowing and clock skew scheduling effects on multi-phase level-sensitive circuits

Timing Optimization Through Clock Skew Scheduling

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