Linear CMOS power amplifiers employing a novel layout configuration for improved stability and long-term reliability

Abe, Kazuhide; Sasaki, Tadahiro; Iida, Atsuko; Itaya, Kazuhiko; Horie, Koji; Nagata, Minoru; Terada, Tomoki P.

doi:10.1109/sirf.2011.5719308

Cited by 4 publications

(3 citation statements)

References 6 publications

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“…We have also reported in another paper that the long-term reliabilities of power amplifiers were improved through optimization of the transistor shapes based on the hypotesis. 9) In this paper, we present additional experimental results that may support our hypothesis.…”

supporting

confidence: 64%

Primary Factor Extracted for Anomalous Decline of Drain Current in Metal–Oxide–Semiconductor Field-Effect Transistors

Abe¹,

Sasaki²,

Itaya³

2012

Jpn. J. Appl. Phys.

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A statistical approach has been exploratively applied to extract an influential factor of anomalous decreases in drain current observed in metal–oxide–semiconductor field-effect transistors with large channel widths. Since negative slopes were detected in drain current vs drain voltage (I d–V ds) curves even with negligible heat quantity or density, the self-heating effect was excluded as the primary factor. In contrast, the aspect ratio of the device areas showed a significant influence. These results support the validity of a hypothesis, namely, that acoustic standing waves are excited and thereby the probabilities of impact ionizations are synchronously magnified in the devices.

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supporting

confidence: 64%

Primary Factor Extracted for Anomalous Decline of Drain Current in Metal–Oxide–Semiconductor Field-Effect Transistors

Abe¹,

Sasaki²,

Itaya³

2012

Jpn. J. Appl. Phys.

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“…Because the large I sub might accelerate hot carrier degradation, it is one of the major issues concerning long-term reliability 9) and stability, 10) particularly acute when the devices are used in power amplifiers. 11,12) In the experimental results reported in Ref. 8, since both the anomalous I sub and I d were always simultaneously detected, the causal relationship between them could not be clarified.…”

mentioning

confidence: 94%

Steep Increase in Substrate Current in Metal–Oxide–Semiconductor Field-Effect Transistor with Multiple-Gate Configuration

Abe

2013

Jpn. J. Appl. Phys.

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A steep increase in substrate current has been observed in a metal–oxide–semiconductor field-effect transistor with a multiple-gate configuration. Regarding gate voltage dependence, the substrate current plotted on a logarithmic scale exhibited a sharp rise with a slope of 6 mV/decade, which is 20 times steeper than that simultaneously measured for the drain current. Since the slope is even 10 times steeper than the ideal subthreshold swing of 60 mV/decade, the upsurge has been discussed using a hypothetical model in which the impact ionization rate is increased by excitation of acoustic standing waves within the device.

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“…Introduction: State-of-art solutions to improve thermal management include optimising the heat dissipation environment, adding heatspreading path [1] and adopting novel power devices or circuits structures. In layout design [2], optimising the cooling environment can be achieved by changing the spacing or length of fingers. In circuit design, the thermal compensation circuits or ballast resistors can be utilised to mitigate the thermal memory effect [3].…”

mentioning

confidence: 99%

Improved thermal management of power cells with adding cooling path from collector to ground

Ting

Sun

Gao³

et al. 2019

Electron. lett.

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A method to improve thermal management of power cells based on gallium arsenide (GaAs) heterojunction bipolar transistors (HBTs) fabricated with backside thermal via (BTV) technology is presented. For common-emitter configuration, collector metal is introduced to provide a new cooling path for heat spreading to BTVs flowing through the insulating layers. Two power cells consist of 64 HBTs, without (T64-A) and with (T64-B) the proposed cooling path are measured by QFI InfraScope TM temperature mapping system. Compared to T64-A, a reduction in the maximum junction temperature (Tj max) of T64-B by 22.55% (40.96°C) is observed when dissipated power (P diss) is 3 W and baseplate temperature (T base) is 25°C. Meanwhile, the thermal distribution of overall power cell is improved, and the improvements are 6.8, 21.67 and 35.96°C at T base = 25°C for three different values of P diss , which are 1, 2 and 3 W, respectively.

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Linear CMOS power amplifiers employing a novel layout configuration for improved stability and long-term reliability

Cited by 4 publications

References 6 publications

Primary Factor Extracted for Anomalous Decline of Drain Current in Metal–Oxide–Semiconductor Field-Effect Transistors

Primary Factor Extracted for Anomalous Decline of Drain Current in Metal–Oxide–Semiconductor Field-Effect Transistors

Steep Increase in Substrate Current in Metal–Oxide–Semiconductor Field-Effect Transistor with Multiple-Gate Configuration

Improved thermal management of power cells with adding cooling path from collector to ground

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