Lightweight Implementations of SHA-3 Candidates on FPGAs

Kaps, Jens-Peter; Yalla, Panasayya; Surapathi, Kishore Kumar; Habib, Bilal; Vadlamudi, Susheel; Gurung, Smriti; Pham, John

doi:10.1007/978-3-642-25578-6_20

Cited by 35 publications

(23 citation statements)

References 15 publications

(25 reference statements)

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“…Compared with SHA-1, SHA-2 will consume some more energy in the hardware implementation [16]. Now, a lot of work has been done to optimize the hardware implementation of SHA-2 and SHA-3 on the resource-constrained hardware platforms [17][18][19][20][21]. For example, when computing a message digest by a SHA-2, the energy consumption is always below 5 J per message block [18].…”

Section: Resultsmentioning

confidence: 99%

A Key Distribution Scheme for WSN Based on Hash Chains and Deployment Knowledge

You

Yuan

et al. 2015

International Journal of Distributed Sensor Networks

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Based on the deployment knowledge and the irreversibility of some hash chains, a novel pairwise key distribution scheme (DKH-KD) for wireless sensor networks is proposed. In DKH-KD scheme, before the nodes in the network are deployed, the offline server constructs a number of hash chains and uses the values from a pair of reverse hash chains to establish their pairwise keys among the nodes in the same region, while, among the neighbor nodes in the different regions, some pairs of the hash chains based on the deployment knowledge are employed to establish the pairwise keys. These procedures make the attackers hard to break the network and ensure that the probability of the pairwise key establishment is close to 1. Compared with the Dai scheme and the q-composite's scheme, our analyses show that DKH-KD scheme can improve the probability of the pairwise key establishment and the invulnerability more efficiently.

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Section: Resultsmentioning

confidence: 99%

A Key Distribution Scheme for WSN Based on Hash Chains and Deployment Knowledge

You

Yuan

et al. 2015

International Journal of Distributed Sensor Networks

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“…In the next clock cycle, the input data is 01, 12, 23, and 30, and the corresponding result is labeled as 01 , 11 (and 21 , and 31 ) and so on. In total 8 clock cycles (clk [25][26][27][28][29][30][31][32] are required to complete the MixColumnsSerial layer using (χ) 2 , 4 clock cycles (clk 9-12 in Table 8) when using (χ) 4 , and 16 clock cycles (clk 9-24 in Table 7) when using (χ), respectively. The next round starts with the SrSc state (clk 9) and inputs 00 and 11 .…”

Section: Serialized Using Srl16smentioning

confidence: 99%

A Very Compact FPGA Implementation of LED and PHOTON

Anandakumar

Peyrin

Pöschmann

2014

Progress in Cryptology -- INDOCRYPT 2014

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Abstract. LED and PHOTON are new ultra-lightweight cryptographic algorithms aiming at resourceconstrained devices. In this article, we describe three different hardware architectures of the LED and PHOTON family optimized for Field-Programmable Gate Array (FPGA) devices. In the first architecture we propose a round-based implementation while the second is a fully serialized architecture performing operations on a single cell per clock cycle. Then, we propose a novel architecture that is designed with a focus on utilizing commonly available building blocks (SRL16). This new architecture, organized in a complex scheduling of the operations, seems very well suited for recent designs that use serial matrices. We implemented both the lightweight block cipher LED and the lightweight hash function PHOTON on the Xilinx FPGA series Spartan-3 (low-cost) and Artix-7 (high-end) devices and our new proposed architecture provides very competitive area-throughput trade-offs. In comparison with other recent lightweight block ciphers, the implementation results of LED show a significant improvement of hardware efficiency and we obtain the smallest known FPGA implementation (as of today) of any hash function.

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“…Highspeed implementations have been reported by J. Strömbergson [39], B. Baldwin et al [3], E. Homsirikamol et al [22], K. Kobayashi et al [31], F. Gürkaynak et al [20], and K. Gaj et al [16,17]. Low-area FPGA designs have been presented by S. Kerckhof et al [29], J.-P. Kaps et al [26], and B. Jungk and J. Apfelbeck [25].…”

Section: Hash Functions For Rfidmentioning

confidence: 99%

Pushing the Limits of SHA-3 Hardware Implementations to Fit on RFID

Pessl

Hutter

2013

Cryptographic Hardware and Embedded Systems - CHES 2013

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Abstract. There exists a broad range of RFID protocols in literature that propose hash functions as cryptographic primitives. Since Keccak has been selected as the winner of the NIST SHA-3 competition in 2012, there is the question of how far we can push the limits of Keccak to fulfill the stringent requirements of passive low-cost RFID. In this paper, we address this question by presenting a hardware implementation of Keccak that aims for lowest power and lowest area. Our smallest (fullstate) design requires only 2 927 GEs (for designs with external memory available) and 5 522 GEs (total size including memory). It has a power consumption of 12.5 µW at 1 MHz on a low leakage 130 nm CMOS process technology. As a result, we provide a design that needs 40 % less resources than related work. Our design is even smaller than the smallest SHA-1 and SHA-2 implementations.

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Lightweight Implementations of SHA-3 Candidates on FPGAs

Cited by 35 publications

References 15 publications

A Key Distribution Scheme for WSN Based on Hash Chains and Deployment Knowledge

A Key Distribution Scheme for WSN Based on Hash Chains and Deployment Knowledge

A Very Compact FPGA Implementation of LED and PHOTON

Pushing the Limits of SHA-3 Hardware Implementations to Fit on RFID

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