Lightweight hardware transactional memory profiling

Wang, Qingsen; Su, Pengfei; Chabbi, Milind; Liu, Xu

doi:10.1145/3293883.3295728

Cited by 5 publications

(2 citation statements)

References 24 publications

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Section: Related Workmentioning

confidence: 99%

“…Lock elision, whether in software or hardware or a hybrid fashion, including gaining insights into them, has been extensively studied [22,29,33,[35][36][37][38]43,44,56,57,62,70,70,71,73,79,89,90,92]. Our work uses many of those techniques; for example, the basic design of our runtime controller was inspired by Wang et al [89]. Additional possibilities to bring more solutions from the literature to the design and implementation of both our static analysis tool and runtime controller also exist.…”

Section: Related Workmentioning

confidence: 99%

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Optimistic Concurrency Control for Real-world Go Programs (Extended Version with Appendix)

Zhang¹,

Chabbi²,

Welc³

et al. 2021

Preprint

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We present a source-to-source transformation framework, GOCC, that consumes lock-based pessimistic concurrency programs in the Go language and transforms them into optimistic concurrency programs that use Hardware Transactional Memory (HTM). The choice of the Go language is motivated by the fact that concurrency is a first-class citizen in Go, and it is widely used in Go programs. GOCC performs rich interprocedural program analysis to detect and filter lock-protected regions and performs AST-level code transformation of the surrounding locks when profitable. Profitability is driven by both static analyses of critical sections and dynamic analysis via execution profiles. A custom HTM library, using perceptron, learns concurrency behavior and dynamically decides whether to use HTM in the rewritten lock/unlock points. Given the rich history of transactional memory research but its lack of adoption in any industrial setting, we believe this workflow, which ultimately produces source-code patches, is more apt for industry-scale adoption. Results on widely adopted Go libraries and applications demonstrate significant (up to 10×) and scalable performance gains resulting from our automated transformation while avoiding major performance regressions.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Optimistic Concurrency Control for Real-world Go Programs (Extended Version with Appendix)

Zhang¹,

Chabbi²,

Welc³

et al. 2021

Preprint

Self Cite

View full text Add to dashboard Cite

show abstract

Analysing software prefetching opportunities in hardware transactional memory

et al. 2021

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A survey on optimizations towards best-effort hardware transactional memory

Lü

Wang

et al. 2020

CCF Trans. HPC

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Transactional memory has been attracting increasing attention in recent years, and it provides optimistic concurrency control schemes for shared-memory parallel programs. The rapid development and wide adoption of transactional memory make this programming paradigm promising for achieving breakthroughs in massively parallel computing. There has been a large number of discussions towards transactional memory systems, which aimed at providing relatively simple and intuitive synchronization construction for shared-memory parallel programs without sacrificing performance. Hardware transactional memory (HTM) has become commercially available in mainstream processors, however, due to several inherent architectural limitations that will abort hardware transactions, such as cache overflows, context switches, hardware as well as software exceptions, etc., nowadays HTM systems come in a best-effort way, which necessitates the adoption of a software fallback path to ensure forward progress. In this paper, we survey state-of-the-art software-side optimizations for best-effort hardware transaction system, as well as several novel performance tuning techniques. Research efforts about joint usage of HTM and non-volatile memory (NVM) are also discussed.

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Lightweight hardware transactional memory profiling

Cited by 5 publications

References 24 publications

Optimistic Concurrency Control for Real-world Go Programs (Extended Version with Appendix)

Optimistic Concurrency Control for Real-world Go Programs (Extended Version with Appendix)

Analysing software prefetching opportunities in hardware transactional memory

A survey on optimizations towards best-effort hardware transactional memory

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