Light-weight communications on Intel's single-chip cloud computer processor

Abstract

Many-core chips are changing the way high-performance computing systems are built and programmed. As it is becoming increasingly difficult to maintain cache coherence across many cores, manufacturers are exploring designs that do not feature any cache coherence between cores. Communications on such chips are naturally implemented using message passing, which makes them resemble clusters, but with an important difference. Special hardware can be provided that supports very fast on-chip communications, reducing latency and increasing bandwidth. We present one such chip, the Single-Chip Cloud Computer (SCC). This is an experimental processor, created by Intel Labs. We describe two communication libraries available on SCC: RCCE and Rckmb. RCCE is a light-weight, minimal library for writing message passing parallel applications. Rckmb provides the data link layer for running network services such as TCP/IP. Both utilize SCC's non-cache-coherent shared memory for transferring data between cores without needing to go off-chip. In this paper we describe the design and implementation of RCCE and Rckmb. To compare their performance, we consider simple benchmarks run with RCCE, and MPI over TCP/IP.

Consensus inside

“…Aublin et al [2] propose ZIMP, a one-to-many communication mechanism for cache-coherent many-cores, addressing situations in which messages need to be broadcast to multiple receivers. In addition, architectures such as Tilera processors [39] and the Intel SCC [38] expose interfaces to some forms of hardwareimplemented message passing, which either complement or replace cache coherence. In QC-libtask, we employ oneto-one communication in order to avoid scalability limitations due to cache line sharing between a large number of cores.…”

An integrated, programming model-driven framework for NoC–QoS support in cluster-based embedded many-cores

“…Regarding MPI, in the industry Intel released its own MPI-based library called RCCE [51,52] which provides message-passing on top of the SCC [2], and IBM explore the possibility to use both, OpenMP [53] and MPI-based [54] on top of the Cell processor. Most of the optimizations proposed in these works are aimed at providing extremely lightweight support for the programming model services, as the target embedded hardware is always constrained in terms of the allowed memory and power consumption, the lack of native operating system services etc.…”

QoS-Driven Reconfigurable Parallel Computing for NoC-Based Clustered MPSoCs

“…In this work, we will focus on message-passing. In the industry, the main example of message-passing is the release of Intel RCCE library [31], [32] which provides message-passing on top of the SCC [6]. IBM also explored the possibility to integrate MPI on the Cell processor [33].…”