Light-OPU

Yu, Yunxuan; Zhao, Tiandong; Wang, Kun; He, Lei

doi:10.1145/3373087.3375311

Cited by 73 publications

(11 citation statements)

References 29 publications

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“…These toolchains just can modify hardware parameter, when timing-closure is not meet, it has to decrease the operating frequency, which leads to performance deterioration. So, Yu et al [25] propose Light-OPU, its toolchain eliminates the re-implementation process. But it doesn't consider the TinyML model situation that all parameters are stored on-chip memory.…”

Section: Introductionmentioning

confidence: 99%

“…BNN [26], [27] use 1-bit weight and activation which dramatically decrease hardware consumption, but it also decreases the accuracy. 8-bits quantization was adopted by [16], [21], [25] which use their own scheme and may deteriorate the accuracy for different CNNs. Currently, TF (TensorFlow) Lite adopts per-channel quantization of weights and per-layer quantization of activations to 8-bits, which produces accuracy loss within 2% compared with floating-point networks for a wide variety of CNN [28].…”

Section: Introductionmentioning

confidence: 99%

“…Copyright c 2021 The Institute of Electronics, Information and Communication Engineers [16], [21], or one certain kernel size [11], [25]. However, upgrading CNN on edge device means accelerator should support more CNNs and the kernel size of different CNN may change.…”

Section: Introductionmentioning

confidence: 99%

“…This is why some accelerators only optimize their architecture on 3×3 kernel size [29]. PE array of [25] just support 3 × 3 kernel, and larger kernel is decomposed into several 3 × 3 kernels which increase computation time.…”

Section: Introductionmentioning

confidence: 99%

“…Temporal reuse isn't fully explored. Temporal reuse doesn't adopt by [21], [25]. Temporal reuse of [12], [22] just adopts a row or a column in IFM (input feature map) at convolution (CONV) layer, not both, and doesn't adopt temporal reuse at fully-connected (FC) layer.…”

Section: Introductionmentioning

confidence: 99%

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HBDCA: A Toolchain for High-Accuracy BRAM-Defined CNN Accelerator on FPGA with Flexible Structure

Gao

Lai

2021

IEICE Trans. Inf. & Syst.

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In recent years FPGA has become popular in CNN acceleration, and many CNN-to-FPGA toolchains are proposed to fast deploy CNN on FPGA. However, for these toolchains, updating CNN network means regeneration of RTL code and re-implementation which is timeconsuming and may suffer timing-closure problems. So, we propose HB-DCA: a toolchain and corresponding accelerator. The CNN on HBDCA is defined by the content of BRAM. The toolchain integrates UpdateMEM utility of Xilinx, which updates content of BRAM without re-synthesis and re-implementation process. The toolchain also integrates TensorFlow Lite which provides high-accuracy quantization. HBDCA supports 8-bits perchannel quantization of weights and 8-bits per-layer quantization of activations. Upgrading CNN on accelerator means the kernel size of CNN may change. Flexible structure of HBDCA supports kernel-level parallelism with three different sizes (3 × 3, 5 × 5, 7 × 7). HBDCA implements four types of parallelism in convolution layer and two types of parallelism in fully-connected layer. In order to reduce access number to memory, both spatial and temporal data-reuse techniques were applied on convolution layer and fully-connect layer. Especially, temporal reuse is adopted at both row and column level of an Input Feature Map of convolution layer. Data can be just read once from BRAM and reused for the following clock. Experiments show by updating BRAM content with single Up-dateMEM command, three CNNs with different kernel size (3 × 3, 5 × 5, 7×7) are implemented on HBDCA. Compared with traditional design flow, UpdateMEM reduces development time by 7.6X-9.1X for different synthesis or implementation strategy. For similar CNN which is created by toolchain, HBDCA has smaller latency (9.97µs-50.73µs), and eliminates re-implementation when update CNN. For similar CNN which is created by dedicated design, HBDCA also has the smallest latency 9.97µs, the highest accuracy 99.14% and the lowest power 1.391W. For different CNN which is created by similar toolchain which eliminate re-implementation process, HBDCA achieves higher speedup 120.28X.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

HBDCA: A Toolchain for High-Accuracy BRAM-Defined CNN Accelerator on FPGA with Flexible Structure

Gao

Lai

2021

IEICE Trans. Inf. & Syst.

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Hardware Architecture of Embedded Inference Accelerator and Analysis of Algorithms for Depthwise and Large-Kernel Convolutions

Chen

Wei²,

Wang³

et al. 2020

Computer Vision – ECCV 2020 Workshops

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In order to handle modern convolutional neural networks (CNNs) efficiently, a hardware architecture of CNN inference accelerator is proposed to handle depthwise convolutions and regular convolutions, which are both essential building blocks for embedded-computer-vision algorithms. Different from related works, the proposed architecture can support filter kernels with different sizes with high flexibility since it does not require extra costs for intra-kernel parallelism, and it can generate convolution results faster than the architecture of the related works. The experimental results show the importance of supporting depthwise convolutions and dilated convolutions with the proposed hardware architecture. In addition to depthwise convolutions with large-kernels, a new structure called DDC layer, which includes the combination of depthwise convolutions and dilated convolutions, is also analyzed in this paper. For face detection, the computational costs decrease by 30%, and the model size decreases by 20% when the DDC layers are applied to the network. For image classification, the accuracy is increased by 1% by simply replacing 3 × 3 filters with 5 × 5 filters in depthwise convolutions.

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Design of Face Detection Algorithm Accelerator Based on Vitis

Wang

Gao

2022

Algorithms and Architectures for Parallel Processing

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Light-OPU

Cited by 73 publications

References 29 publications

HBDCA: A Toolchain for High-Accuracy BRAM-Defined CNN Accelerator on FPGA with Flexible Structure

HBDCA: A Toolchain for High-Accuracy BRAM-Defined CNN Accelerator on FPGA with Flexible Structure

Hardware Architecture of Embedded Inference Accelerator and Analysis of Algorithms for Depthwise and Large-Kernel Convolutions

Design of Face Detection Algorithm Accelerator Based on Vitis

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