Lifetime of CMOS circuits evaluation by means of electro-thermal simulations

Abstract

An electro-thermal compact model of MOSFET which takes the hot carriers effects into account is presented in this paper. This new compact model evaluates the threshold voltage shift as well as the mobility reduction induced by the increase of the density of states at the Si/SiO 2 interface produced by hot carriers. This physical effect depends on the biasing conditions and the temperature of the device. Results obtained on a single transistor are presented and compared to experimental results. Electro-thermal simulations at chip level are presented through a circuit dedicated to effective aging evaluation. Simulation results clearly show how the temperature reduces the lifetime of circuits. This new electro-thermal compact model coupled to our electro-thermal simulation tool offers the possibility to evaluate the lifetime of analog CMOS circuit.