Leveraging Transverse Reads to Correct Alignment Faults in Domain Wall Memories

Ollivier, Sébastien; Kline, Donald W.; Roxy, Kawsher A.; Melhem, Rami; Banja, Sanjukta; Jones, Alex K.

doi:10.1109/dsn.2019.00047

Cited by 18 publications

(10 citation statements)

References 40 publications

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“…We will see how TRD = 7 is particularly effective for addition. TRD = 7, while optimistic, is significantly more realistic than the presumed TRD = 32 assumed in prior work [20].…”

Section: A Pirm Architecturementioning

confidence: 79%

“…This inherent behavior of DWM can be imprecise, generating what is known as a "shifting fault" in the literature. Several solutions have been proposed to mitigate this fault mode [20]- [22].…”

Section: A Domain-wall Memory Fundamentalsmentioning

confidence: 99%

“…TR was recently proposed [17] and leveraged to improve reliability via detection and correction of over/under-shifting faults [20]. TR is akin to using a portion of a DWM nanowire Fig.…”

Section: Transverse Readmentioning

confidence: 99%

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PIRM: Processing In Racetrack Memories

Ollivier¹,

Longofono²,

Dutta³

et al. 2021

Preprint

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The growth in data needs of modern applications has created significant challenges for modern systems leading a "memory wall." Spintronic Domain-Wall Memory (DWM), related to Spin-Transfer Torque Memory (STT-MRAM), provides near-SRAM read/write performance, energy savings and nonvolatility, potential for extremely high storage density, and does not have significant endurance limitations. However, DWM's benefits cannot address data access latency and throughput limitations of memory bus bandwidth. We propose PIRM, a DWM-based in-memory computing solution that leverages the properties of DWM nanowires and allows them to serve as polymorphic gates. While normally DWM is accessed by applying spin polarized currents orthogonal to the nanowire at access points to read individual bits, transverse access along the DWM nanowire allows the differentiation of the aggregate resistance of multiple bits in the nanowire, akin to a multilevel cell. PIRM leverages this transverse reading to directly provide bulk-bitwise logic of multiple adjacent operands in the nanowire, simultaneously. Based on this in-memory logic, PIRM provides a technique to conduct multi-operand addition and two operand multiplication using transverse access. PIRM provides a 1.6× speedup compared to the leading DRAM PIM technique for query applications that leverage bulk bitwise operations. Compared to the leading PIM technique for DWM, PIRM improves performance by 6.9×, 2.3× and energy by 5.5×, 3.4× for 8-bit addition and multiplication, respectively. For arithmetic heavy benchmarks, PIRM reduces access latency by 2.1×, while decreasing energy consumption by 25.2× for a reasonable 10% area overhead versus non-PIM DWM.

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“…We will see how TRD = 7 is particularly effective for addition. TRD = 7, while optimistic, is significantly more realistic than the presumed TRD = 32 assumed in prior work [20].…”

Section: A Pirm Architecturementioning

confidence: 79%

Section: A Domain-wall Memory Fundamentalsmentioning

confidence: 99%

See 1 more Smart Citation

PIRM: Processing In Racetrack Memories

Ollivier¹,

Longofono²,

Dutta³

et al. 2021

Preprint

Self Cite

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show abstract

“…In these cases, the entire nanowire uniformly shifts by an incorrect amount. Error correction codes (ECC) alone are insufficient to detect and correct these faults [9] but existing schemes have been proposed to address misalignment resulting in meantime-to-failure (MTTF) on the order of decades [8], [9].…”

Section: Motivationmentioning

confidence: 99%

“…Thus, shift fault characterization from process variation must be characterized to allow DWM designs to appropriately tradeoff efficiency and reliability. There has been significant effort on power reduction and speed improvement [4]- [7] to optimize DWM shifting overhead; relatively fewer efforts [8], [9] focus on shift reliability due in part to insufficient error-modeling, which we address here.…”

mentioning

confidence: 99%

Pinning Fault Mode Modeling for DWM Shifting

Roxy

Longofono

Olliver

et al. 2022

IEEE Trans. Circuits Syst. II

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Extreme scaling for purposes of achieving higher density and lower energy continues to increase the probability of memory faults. For domain wall (DW) memories, misalignment faults arise when aligning domains with access points. A previously understudied type of shifting fault, a pinning fault may occur due to non-uniform pinning potential distribution caused by notches with fabrication imperfections. This non-uniformity can pin a wall during current-induced DW motion. This paper provides a model of geometric variations varying width, depth, and curvature variations of a notch, their impacts on the critical shift current, and a study of the resulting impact on fault rates of DW memory systems. An increase in the effective critical shift current due to 5% variation predicts a pinning fault rate on the order of 10 −8 per shift, which results in a mean-time-to-failure of circa 2s for a DW memory system.

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Position error-free control of magnetic domain-wall devices via spin-orbit torque modulation

Lee,

Kim,

Whang

et al. 2023

Nat Commun

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Magnetic domain-wall devices such as racetrack memory and domain-wall shift registers facilitate massive data storage as hard disk drives with low power portability as flash memory devices. The key issue to be addressed is how perfectly the domain-wall motion can be controlled without deformation, as it can replace the mechanical motion of hard disk drives. However, such domain-wall motion in real media is subject to the stochasticity of thermal agitation with quenched disorders, resulting in severe deformations with pinning and tilting. To sort out the problem, we propose and demonstrate a new concept of domain-wall control with a position error-free scheme. The primary idea involves spatial modulation of the spin-orbit torque along nanotrack devices, where the boundary of modulation possesses broken inversion symmetry. In this work, by showing the unidirectional motion of domain wall with position-error free manner, we provide an important missing piece in magnetic domain-wall device development.

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Leveraging Transverse Reads to Correct Alignment Faults in Domain Wall Memories

Cited by 18 publications

References 40 publications

PIRM: Processing In Racetrack Memories

PIRM: Processing In Racetrack Memories

Pinning Fault Mode Modeling for DWM Shifting

Position error-free control of magnetic domain-wall devices via spin-orbit torque modulation

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