Leveraging QDI Robustness to Simplify the Design of IoT Circuits

Abstract

Internet of Things devices require innovative power efficient design techniques that ensure correct operation in harsh environments, where using synchronous design can be challenging. The timing sign-off of synchronous circuits requires analysis and optimisation under multiple corners and operating modes. Considering that energy efficient circuits demand dynamic voltage ranges and harsh environments impose significant variations, design sign-off may become prohibitively expensive. An alternative is quasi-delay-insensitive asynchronous design, which presents robustness against timing variations, simplifying timing sign-off. This paper leverages recent developments in asynchronous circuits design automation to achieve higher degrees of energy efficiency using voltage scaling, while ensuring solid robustness to variability.

Quasi Delay Insensitive FIFOs: Design Choices Exploration and Comparison

“…Power efficiency improves when supply voltage reduces [16]. QDI circuits are highly tolerant to supply downscaling, as recently demonstrated [17]. Figure 4 shows the voltage scaling impact, with results of multiple simulations run over a range of supplies, from 0.3 V to 1.0 V, in 100 mV steps.…”

Robust and Energy-Efficient Hardware: The Case for Asynchronous Design

“…The results in this Section were extracted from [67]. To build asynchronous QDI circuits up to the layout level, Pulsar relies on a series of standard cell libraries containing SDDS-NCL cells, all developed by the authors' research group for several technology nodes.…”

Components to Support Choice in Self-Timed Asynchronous Design Flows

“…The latter reduces the crossed timing dependence between data and control lines, and the number of implied relative timing constraints to solve. Demonstrations, even if partial, that the advantage takes place in practical circuits designed with Pulsar is available in previously published work, including [5], [6], [30], [31].…”

“…If alternative design techniques can guarantee automatic adaptability of the circuit to the level of voltage scaling, the overhead caused by such techniques can be avoided. As an example, Sartori et al in [5] describe an experiment towards such an alternative, where an asynchronous class of design techniques called self-timed design demonstrates to be resilient to voltage scaling, allowing correct operation of circuits over a wide range of supply voltages, from nominal to sub-threshold.…”

“…A spacer is in fact associated to one of the unused or invalid bit configurations (those not used to represent data) and is meant to explicitly indicate the absence of data in a data channel. In the example here, the single bit DI code states that 01 means a '0' bit value, 10 means a '1' bit value, 00 is the spacer and 11 has no meaning and should never occur as a stable value 5. The use of the latch term in asynchronous circuits and their token flow model representation is associated to the general notion of a temporal barrier, and it does not necessarily imply a specific physical implementation 6.…”