Leti-UTSOI2.1: A Compact Model for UTBB-FDSOI Technologies—Part I: Interface Potentials Analytical Model

Poiroux, T.; Rozeau, O.; Scheer, P.; Martinie, S.; Jaud, Marie-Anne; Minondo, M.; Juge, André; Barbé, J. C.; Vinet, M.

doi:10.1109/ted.2015.2458339

Cited by 44 publications

(18 citation statements)

References 24 publications

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“…Given these facts, it is more objective to present the methodology for the design of a circuit with only model generated parasitic capacitance take into account and, perhaps, a representation of a few interconnect parasitic capacitances at critical nodes. For these reasons, the presented algorithms take into account only parasitic capacitances predicted by the CEA-Leti UTSOI2.1 transistor model [23], [24]. Regardless of the afore-mentioned reasons, there is a possi- for each passed TF do…”

Section: A Components Of the Proposed Design Methodologymentioning

confidence: 99%

A g_m/I_D Methodology Based Data-Driven Search Algorithm for the Design of Multistage Multipath Feed-Forward-Compensated Amplifiers Targeting High Speed Continuous-Time ΣΔ-Modulators

Gebreyohannes

Porte

Louërat

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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This work presents a methodology for sizing transistors of a multi-stage, multi-path capacitor-less feed-forward compensated operational amplifiers employed in advanced CMOS process implementation of continuous-time bandpass Σ∆modulators. The paper describes the methodology: on system level, dealing with the placement of poles and zeros; and on circuit level, discussing issues related to biasing, frequency response and other important performance metrics of the basic diffpair. Algorithms are provided to simplify mathematical aspects of the work. The validity and the limitations of the proposed methodology are further discussed from the single-pole system used to model the individual amplification stages of the multistage amplifier. The worthiness of the proposed methodology in sizing the transistors of complex amplifier structures such as the capacitor-less multi-stage, multi-path feed-forward-compensated amplifiers is demonstrated using two design examples. A 3 rdorder amplifier with a DC gain of 52.6 dB and that reaches a unity-gain frequency of above 14 GHz while consuming only 5.6 mA from a 1 V supply; and a 4 th-order amplifier with DC gain of 73.5 dB that achieves a 25.7 dB gain at 1 GHz while consuming 4.8 mW are designed in 28nm CMOS FDSOI.

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Section: A Components Of the Proposed Design Methodologymentioning

confidence: 99%

A g_m/I_D Methodology Based Data-Driven Search Algorithm for the Design of Multistage Multipath Feed-Forward-Compensated Amplifiers Targeting High Speed Continuous-Time ΣΔ-Modulators

Gebreyohannes

Porte

Louërat

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Accurate surface potentials for IDG MOSFET have been proposed in [14]- [17]. However, those methods are applicable to only free carriers or need iterative resolution of the Poisson equation.…”

Section: A Surface Potential Calculationmentioning

confidence: 99%

Analytical Surface Potential-Based Compact Model for Independent Dual Gate a-IGZO TFT

Guo

Zhao

Yang

et al. 2021

IEEE Trans. Electron Devices

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A surface potential-based compact model for independent dual gate (IDG) amorphous In-Ga-Zn-O thinfilm transistors (IDG a-IGZO TFTs) is proposed here. The transport theories of percolation conduction, trap-limited conduction (TLC), and variable range hopping (VRH) in extended and localized states are first considered simultaneously via Schroder method, obtaining a physical description of the transport mechanism under different conditions of temperature and gate voltage. Moreover, a single formulation of front and back surface potentials which is valid and extremely accurate in all operation regimes is developed.Based on the transport theories and surface potentials, the complete compact model is developed and verified using both numerical simulation and experiment with an excellent agreement, and the threshold compensation effect is also included. Finally, the compact model is coded in Verilog-A, and implemented in a vendor CAD environment, which suggested that the proposed model can be successfully applied to circuit design. Index Terms-Analytical models, independent dual gate (IDG) amorphous In-Ga-Zn-O thin-film transistors (IDG a-IGZO TFTs), Schroder method, surface potential, threshold compensation effect.

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“…The ILD serves as the buried oxide (BOX) of the SOI devices. CEA-LETI's UTSOI2.1 model for ultra thin body SOIs is used for these devices, [9], [10]. The relatively thick (500 nm) ILD minimizes the coupling between the two tiers as this is described in [11].…”

Section: B Device Modelsmentioning

confidence: 99%

Enabling area efficient RF ICs through monolithic 3D integration

Chaourani

Hellstrcom

Rodriguez

et al. 2017

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

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Abstract-The Monolithic 3D (M3D) integration technology has emerged as a promising alternative to dimensional scaling thanks to the unprecedented integration density capabilities and the low interconnect parasitics that it offers. In order to support technological investigations and enable future M3D circuits, M3D design methodologies, flows and tools are essential. Prospective M3D digital applications have attracted a lot of scientific interest. This paper identifies the potential of M3D RF/analog circuits and presents the first attempt to demonstrate such circuits. Towards this, a M3D custom design platform, which is fully compatible with commercial design tools, is proposed and validated. The design platform includes process characteristics, device models, LVS and DRC rules and a parasitic extraction flow. The envisioned M3D structure is built on a commercial CMOS process that serves as the bottom tier, whereas a SOI process is used as top tier. To validate the proposed design flow and to investigate the potential of M3D RF/analog circuits, a RF front-end design for Zig-Bee WPAN applications is used as case-study. The M3D RF front-end circuit achieves 35.5 % area reduction, while showing similar performance with the original 2D circuit.

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Leti-UTSOI2.1: A Compact Model for UTBB-FDSOI Technologies—Part I: Interface Potentials Analytical Model

Cited by 44 publications

References 24 publications

A g_m/I_D Methodology Based Data-Driven Search Algorithm for the Design of Multistage Multipath Feed-Forward-Compensated Amplifiers Targeting High Speed Continuous-Time ΣΔ-Modulators

A g_m/I_D Methodology Based Data-Driven Search Algorithm for the Design of Multistage Multipath Feed-Forward-Compensated Amplifiers Targeting High Speed Continuous-Time ΣΔ-Modulators

Analytical Surface Potential-Based Compact Model for Independent Dual Gate a-IGZO TFT

Enabling area efficient RF ICs through monolithic 3D integration

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Leti-UTSOI2.1: A Compact Model for UTBB-FDSOI Technologies—Part I: Interface Potentials Analytical Model

Cited by 44 publications

References 24 publications

A gm/ID Methodology Based Data-Driven Search Algorithm for the Design of Multistage Multipath Feed-Forward-Compensated Amplifiers Targeting High Speed Continuous-Time ΣΔ-Modulators

A gm/ID Methodology Based Data-Driven Search Algorithm for the Design of Multistage Multipath Feed-Forward-Compensated Amplifiers Targeting High Speed Continuous-Time ΣΔ-Modulators

Analytical Surface Potential-Based Compact Model for Independent Dual Gate a-IGZO TFT

Enabling area efficient RF ICs through monolithic 3D integration

Contact Info

Product

Resources

About

A g_m/I_D Methodology Based Data-Driven Search Algorithm for the Design of Multistage Multipath Feed-Forward-Compensated Amplifiers Targeting High Speed Continuous-Time ΣΔ-Modulators

A g_m/I_D Methodology Based Data-Driven Search Algorithm for the Design of Multistage Multipath Feed-Forward-Compensated Amplifiers Targeting High Speed Continuous-Time ΣΔ-Modulators