LETHOR: a thermal-aware proactive routing algorithm for 3D NoCs with less entrance to hot regions

Safari, Maede; Shirmohammadi, Zahra; Rohbani, Nezam; Farbeh, Hamed

doi:10.1007/s11227-021-04207-3

Cited by 2 publications

(1 citation statement)

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“…Thermal issues make systems more vulnerable to temperature effects such as reliability, leakage and delay [9]. To balance temperature distribution various methods have been proposed such as, floor-plan optimization [10], [11], thermal-aware application mapping [12], and thermal-aware routing [13], [14]. There are two types of thermal-aware routing algorithms, temporal thermalaware routing algorithms and spatial thermal-aware routing algorithms.…”

Section: Introductionmentioning

confidence: 99%

Thermal-aware directional and adaptive routing algorithm for 3D network-on-chip

Kaleem

Isnin

2022

IJEECS

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Due to the tier architecture <span lang="EN-US">of 3D network-on-chip (3D-NoC), reducing the thermal hotspot within the chip is challenging as a cooling mechanism that lies merely on the single side of a chip. High power density in 3D NoC is responsible for reliability degradation and thermal difficulties. Thermal-aware routing becomes substantial to handle thermal difficulties and diffusion of heat to the cooler regions. Thermal-aware routing focuses on bypassing hotspot areas by selecting cooler areas. Existing thermal-aware routing algorithms adopt slightly cooler but longer and extended paths, due to lack of ability to know the proximity of the destination's location, which aggravate thermal issues. This work presents a novel thermal-aware directional and adaptive routing algorithm. Objective of the proposed algorithm is to strive to find the best possible neighbour to reach closer to the proximity of the destination. The proposed algorithm can adaptively choose any suitable neighbour that can lead packets closer to the destination at each intermediate node. The performance of the proposed algorithm is evaluated and compared with existing thermal-aware routing algorithm in a simulator environment. Simulation results demonstrate that the proposed method outperformed its counterpart in terms of average delay with 11-26% improvement, total hop counts with 8-24% reduction under various traffic conditions and improvement in overall thermal profiling of the chip.</span>

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