Length-constrained escape routing of differential pairs

Yan, Jin-Tai

doi:10.1016/j.vlsi.2014.07.006

Cited by 5 publications

(2 citation statements)

References 9 publications

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“…Many studies in the literature have proposed solutions for escape routing problem among which some have considered single layer (Lei & Mak, 2015) in the PCB while, multiple layers (Bayless, Hoos & Hu, 2016, Zhang et al, 2015a have also been considered. There are studies that only consider escape routing (McDaniel, Grissom & Brisk, 2014) while, there are some studies which consider other problems like length matching (Zhang et al, 2015b, Yan, 2015, Chang, Wen & Chang, 2019 along with the escape routing as well. Some have used staggered pin array (Ho, Lee & Chang, 2013; while others have used grid pin array (Jiao & Dong, 2016) as well.…”

Section: Related Workmentioning

confidence: 99%

A dual model node based optimization algorithm for simultaneous escape routing in PCBs

Ali

Anjum

Zeeshan

2021

PeerJ Computer Science

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Simultaneous Escape Routing (SER) is the escaping of circuit pins simultaneously from inside two or more pin arrays. This is comparatively difficult as compared to routing in a single array and has not been addressed by previous studies. The increase in pin array complexity has made the manual SER in PCBs a very inefficient and tedious task and there surely is need for the automated routing algorithms. In this work, we propose network flow based optimal algorithm that uses integer linear program to solve SER problem and area routing problem in two stages. In the first stage, pins are escaped to the boundaries of pin arrays simultaneously. These escaped pins are connected with each other in the second stage. The proposed algorithm is tested for different benchmark sizes of grids and the results show that it is not only better in terms of routability but also outperforms existing state of the art algorithms in terms of time consumption. The existing algorithms either fails to achieve higher routability or have larger time complexities, whereas the proposed algorithm achieves 99.9% routability and is also independent of grid topology and component pin arrangement, which shows the superiority of proposed algorithm over the existing algorithms.

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Section: Related Workmentioning

confidence: 99%

A dual model node based optimization algorithm for simultaneous escape routing in PCBs

Ali

Anjum

Zeeshan

2021

PeerJ Computer Science

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“…Escape routing can be divided into three types [18]: (i) Unordered escape routing where pins of a single component are routed to the component boundary without considering any specific escape order of the pins [19][20][21][22][23]; (ii) Ordered escape routing where pins of one component are escaped in a pre-defined order. Bus escape, also referred as maximum disjoint subset problem [24] is another example of this type of routing; and (iii) Simultaneous escape routing where pins of two components are escaped simultaneously, ensuring that the nets of both components are escaped in same order.…”

Section: Related Workmentioning

confidence: 99%

Simultaneous Escape Routing using Network Flow Optimization

Sattar

Ignjatović

2016

MJCS

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With the advancement in technology, the size of electronic components and printed circuit boards (PCB) is becoming small while the pin count of each component is increasing. This has necessitated the use of ball grid array (BGA) type of components where pins are attached under the body of component as a grid. The problem of routing pins from under the body of component to the boundary of the component is known as escape routing. It is often desirable to perform ordered simultaneous escape routing (SER) to facilitate area routing and produce elegant PCB design. The task of SER is non-trivial, given the small size of components and hundreds of pins arranged in random order in each component that needs ordered connectivity. In this paper, first we propose flow models for different inter pin capacities. We then propose linear network flow optimization model that simultaneously solves the net ordering and net escape problem. The model routes maximum possible nets between two components of the PCB, by considering the design rules. Comparative analysis shows that the proposed optimization model performs better than the existing routing algorithms in terms of number of nets routed.

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