Left to right serial multiplier for large numbers on FPGA

VLSI Implementation of a High Speed Multiplier Using on the Fly Conversion Technique

“…A Left-To-Right Array multiplier can be implemented by separation of lower and upper partial products which were structured to get the output at less time. This will take a same amount of time required to implement the tree based multiplier [7].A high speed full adder is implemented using the EX-NOR gate technique and PTL logic to implement the circuit.Time required to get the output will be drastically reduced by using the PTL logic design of the adder circuits,Which also reduces the power required to implement the circuit whiuch can be added as an advantage for the bigger circuits where it is involved [6].The sum which the adders depended will relates a major source to get the output .The structure of sum can be modified and rebuild to get the output using less number of gates .The carry will also be effected by the circuit of sum [8].The multiplier using the dadda Algorithm which redefines the structure of the partial products .The stages of partial products will be reconfigured to get the simplified structure to implement the multiplication process.Each stage of partial products will be reduced using different stages and implemented using less number of gates [9].The advantage of C-CMOS logic is that robustness of voltage scaling and transistor sizing. But the disadvantage is that requirement of buffers.The design of full adders were done using the provided logics namely Transmission gate full adder(TGA), complimentary pass transistor logic (CPL), static complimentary metal-oxide-semiconductor (CMOS), dynamic CMOS, transmission function full adder (TFA),Pass transistors Logic(PTL).From the logics the Ptl logic can be best suitable for implementation of adders [10], [11].A full adder has implemented using the CMOS technology and Transmission gate technology which produced a high swing outputs [9].The new design for the full adder using X-OR AND X-NOR implemented which has been resulted in reducing the delay with 43% when compared with the existing adders [11] .The usage of major component in multiplier is an adder and has implemented majorly using the CMOS technology.…”

Single and multiple precision sequential large multipliers for field-programmable gate arrays

“…The recent work on the design of large multipliers focuses on field-programmable gate array (FPGA) implementations due to their rapid design and flexibility advantages [5][6][7][8][9][10][11][12]. A brief discussion of the previous work is provided.…”

“…In [8], a bit serial large multiplier design is presented. The design uses carry save adders to perform the addition of partial product bits.…”

“…Quan et al [5] and Athow and Al-Khalili's [7] designs use excessive amounts of hardware resources. The multiplier proposed by Bessalah et al [8] can support 1024-bit multiplication, but is extremely slow. The designs reported in Banescu et al [9] and in Jaiswal and Cheung [10] are the fastest, but they are designed for floating point multiplication and they cannot multiply operands larger than 130 bits.…”