Learn the Switches: Evolving FPGA NoCs with Stall-Free and Backpressure Based Routers

Malik, Gurshaant; Lang, Ian Elmor; Pellizoni, Rodolfo; Kapre, Nachiket

doi:10.1109/fpl50879.2020.00015

Cited by 2 publications

(5 citation statements)

References 15 publications

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“…We now discuss two speciic advantages of learning unique regulation rates for every trace in the lowset, speciic to the applications and QoR at hand. We contrast this proposed learning approach against the practice of using a single rate to regulate all traces within a lowset [5,17].…”

Section: Learning Regulation Ratesmentioning

confidence: 99%

“…The sample that best optimises for the requested QoR can be selected as the desired regulation rate. This is equivalent to the linear search of [17] and section 6.2.1 (learning only switch conigurations) ∈ (0,1], with NoC routability measured as a function of the regulation rate. The precision of the linear search increments can be ine-grained to support 32 bit regulators instead of the chunkier increments of the original work.…”

Section: Univariate Rate Learningmentioning

confidence: 99%

“…Recall that each trace in a lowset can impact the others via second order interactions and we encode this dependence by modelling as a multivariate gaussian distribution ∼ N (, 2 ), with ∈ [0, 1] and ∈ [0, 1] . This is a key diferentiation between univariate of section 5.2.1 and [17] as it allows us to extract crucial information about these interactions. Furthermore, increasing the dimension of the regulation search space allows us to directly address bottlenecks in NoC routing by: 1. learning the regulation rates of the most diicult traces in an application as well as 2. encode this information in rates of traces that might be involved in indirect interactions.…”

Section: Multivariate Rate Learningmentioning

confidence: 99%

“…Since we keep halving the rate until feasibility is achieved, the time complexity is logarithmic in nature; taking only |log 2 ()| steps to ind the irst feasible rate . A simple search, as used in [17], exhibits linear asymptotic time complexity in contrast; taking…”

Section: Nested Learningmentioning

confidence: 99%

“…Regulation is an important variable in the Hoplite suits of analysis tools to guarantee tight bounds on routing latency and NoC costs. Previous versions of Hoplite [5,17] leave regulation rate out of the decision space as a user parameter; evaluating NoC designs by measuring performance over a range between [0,1] with a ixed increment linear search. Furthermore, only a single regulation rate is used to regulate all traces in an application lowset, which can create unintended bottlenecks in NoC routing and distort search spaces of other NoC parameters.…”

Section: Introductionmentioning

confidence: 99%

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HopliteML: Evolving Application Customized FPGA NoCs with Adaptable Routers and Regulators

Malik

Lang

Pellizzoni

et al. 2022

ACM Trans. Reconfigurable Technol. Syst.

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We can overcome the pessimism in worst-case routing latency analysis of timing-predictable Network-on-Chip (NoC) workloads by single digit factors through the use of a hybrid FPGA-optimized NoC and workload adapted regulation. Timing-predictable FPGA-optimized NoCs such as HopliteBuf integrate stall-free FIFOs that are sized using offline, static analysis of a user-supplied flow pattern and rates. For certain bursty traffic and flow configurations, the static analysis delivers very large, sometimes infeasible, FIFO size bounds and large worst-case latency bounds. Alternatively, backpressure-based NoCs such as HopliteBP can operate with lower latencies for certain bursty flows. However, they suffer from severe pessimism in the analysis due to the effect of pipelining of packets and interleaving of flows at switch ports. As we show in this paper, a hybrid FPGA NoC that seamlessly composes both design styles on a per-switch basis, delivers the best of both worlds with improved feasibility (bounded operation), and tighter latency bounds. We select the NoC switch configuration through a novel evolutionary algorithm based on Maximum Likelihood Estimation (MLE). For synthetic ( RANDOM , LOCAL ) and real world ( SpMV , Graph ) workloads, we demonstrate ≈ 2–3 × improvements in feasibility, ≈ 1–6.8 × in worst-case latency while only requiring LUT cost ≈ 1–1.5 × larger than the cheapest HopliteBuf solution. We also deploy and verify our NoC (PL) and MLE framework (PS) on a Pynq-Z1 to adapt and reconfigure NoC switches dynamically. We can further improve a workload’s routability by learning to surgically tune regulation rates for each traffic trace to maximise available routing bandwidth. We capture critical dependency between traces by modelling the regulation space as a multivariate gaussian distribution and learn the distribution’s parameters using Covariance Matrix Adaptation Evolution Strategy (CMA-ES). We also propose nested learning that learns switch configurations and regulation rates in-tandem. Compared to standalone switch learning, this symbiotic nested learning helps achieve ≈ 1.5 × lower cost constrained latency, ≈ 3.1 × faster individual rates and ≈ 1.4 × faster mean rates. We also evaluate improvements to vanilla NoCs’ routing using only standalone rate learning (no switch learning); with ≈ 1.6 × lower latency across synthetic and real world benchmarks.

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Section: Learning Regulation Ratesmentioning

confidence: 99%

Section: Univariate Rate Learningmentioning

confidence: 99%

Section: Multivariate Rate Learningmentioning

confidence: 99%

Section: Nested Learningmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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