Leaky Wires

Giechaskiel, Ilias; Rasmussen, Kasper; Eguro, Ken

doi:10.1145/3196494.3196518

Cited by 60 publications

(18 citation statements)

References 30 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Another remote side-channel attack [43] is demonstrated on the multi-tenant use of FPGAs. In addition, there are attacks [31,52] capable of stealing information from a victim accelerator through the interference between neighbouring two wires used by the victim and attacker. For mounting such attacks on the cloud, its infrastructure has to be known, i.e.…”

Section: Attacker Capabilitiesmentioning

confidence: 99%

See 1 more Smart Citation

Trust in FPGA-accelerated Cloud Computing

Turan

Verbauwhede

2020

ACM Comput. Surv.

View full text Add to dashboard Cite

Platforms combining Central Processing Systems (CPUs) with Field Programmable Gate Arrays (FPGAs) have become popular, as they promise high performance with energy efficiency. This is the result of the combination of FPGA accelerators tuned to the application, with the CPU providing the programming flexibility. Unfortunately, the security of these new platforms has received little attention: The classic software security assumption that hardware is immutable no longer holds. It is expected that attack surfaces will expand and threats will evolve, hence the trust models, and security solutions should be prepared. The attacker model should be enhanced and consider the following three basic entities as the source of threats: applications run by users, accelerators designed by third-party developers, and the cloud service providers enabling the computation on their platforms. In our work, we review current trust models and existing security assumptions and point out their shortcomings. We survey existing research that target secure remote FPGA configuration, the protection of intellectual property, and secure shared use of FPGAs. When combined, these are the foundations to build a solution for secure use of FPGAs in the cloud. In addition to analysing the existing research, we provide discussions on how to improve it and disclose various concerns that have not been addressed yet.

show abstract

Section: Attacker Capabilitiesmentioning

confidence: 99%

“…For example, different directions of the propagation of clock signal may result into observable effects on the timing. In addition, complete isolation of regions should be achievable, so that interference between them and related attacks [31,52] can be prevented.…”

Section: Shared Use Of Fpgasmentioning

confidence: 99%

Trust in FPGA-accelerated Cloud Computing

Turan

Verbauwhede

2020

ACM Comput. Surv.

View full text Add to dashboard Cite

show abstract

“…1) We show that the long wire leakage phenomenon persists in the Virtex UltraScale+ FPGA family found in many Xilinx-based cloud providers [23]. As we explain in Section II, UltraScale+ long wires differ significantly from those investigated in prior work [4], [5]. 2) We introduce a novel flip-flop-based RO and also evaluate a latch-based RO, both of which overcome combinatorial loop restrictions.…”

Section: Introductionmentioning

confidence: 98%

“…With the availability of FPGAs in public cloud infrastructures rapidly rising, and with FPGA designs becoming more sophisticated, several security concerns arise from the prospect of multi-tenant FPGA usage. IP core integration from multiple sources [4], [5], [13], shared FPGA resources between different users [4], [5], [9], [13], [16], [24], and CPU/FPGA hybrid designs [4], [5] enable previously-unexplored attacks, without the need for physical access to the FPGA boards.…”

Section: Introductionmentioning

confidence: 99%

“…ROs have also been used to cause fault attacks and recover cryptographic keys [10], or as sensors for covert channels [20] and side-channel attacks, even for designs with logical isolation enabled [25]. Recent work has also discovered that so-called long wires in Xilinx [4], [5] and Intel [13], [16] This work was supported in part by NSF grants 1716541 and 1901901. We would also like to thank Amazon for donating AWS EC2 research credits.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Measuring Long Wire Leakage with Ring Oscillators in Cloud FPGAs

Giechaskiel

Rasmussen

Szefer

2019

2019 29th International Conference on Field Programmable Logic and Applications (FPL)

Self Cite

View full text Add to dashboard Cite

Recent investigations into FPGA routing resources have shown that long wires in FPGAs leak information about their state in a way which can be measured using ring oscillators. Although in many cases this leakage does not pose a security threat, the possibility of multi-tenant use of FPGA resources invites potential side-and covert-channel attacks exploiting long wire leakage. However, prior work has ignored the realities of cloud environments, which may pose restrictions on the generated bitstreams, such as disallowing combinatorial loops. In this paper, we first demonstrate that the long wire leakage phenomenon persists even in the high-end Virtex UltraScale+ FPGA family. We then evaluate two ring oscillator designs that overcome combinatorial loop restrictions employed by cloud FPGA providers. We experimentally measure the long wire leakage of Virtex UltraScale+ FPGAs in the lab as well as in the Amazon and Huawei FPGA clouds. We show that the two new ring oscillator designs provide almost-identical estimates for the strength of the leakage as traditional ring oscillators, allowing us to measure femtosecond-scale changes in the delays of the long wires. We finally present a set of defense mechanisms that can prevent the new ring oscillator designs from being instantiated in the cloud and the long wire leakage from being exploited.

show abstract