Leakage Reduction by Using FinFET Technique for Nanoscale Technology Circuits

Dadoria, Ajay Kumar; Khare, Kavita; Gupta, Tarun Kumar; Singh, Rajendra Prasad

doi:10.1166/jno.2017.2002

Cited by 8 publications

(6 citation statements)

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“…This permits the execution and simulation of transistor applications in a faster way both in analog as well as digital domains. FinFET seems to be a better option for the future nano electronics because of its following characteristics such as compact susceptibility, high performance, minimized manufacturing costs and low power consumption [17][18]. The bulkCMOS transistors can be replaced by means of FinFETs [19].…”

Section: Finfet Technologymentioning

confidence: 99%

A Review On Sram Memory Design Using Finfet Technology

Lakshmi¹,

Kamaraju²

2022

Preprint

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An innovative technology named FinFET (Fin Field Effect Transistor) has been developed to offer better transistor circuit design and to balance the necessity of superior storage system (SS). As gate loses control over the channel, CMOS devices face some major issues like increase in manufacturing cost, less reliability and yield, increase of ON current, short channel effects (SCEs), increase in leakage currents etc. However, the memory must have less power dissipation, short access time and low leakage current. The traditional design of SRAM (Static RAM) using CMOS technology represents severe performance degradation due to its higher power dissipation and leakage current. Thus, a Nano-scaled device named FinFET is introduced for designing SRAM since it has three dimensional (3D) design of the gate. FinFET has been used to improve the overall performance, which includes efficiency, power, and area. Moreover, FinFET has been chosen as a transistor of choice because it is not affected by SCEs. In this work, we have reviewed various FinFET based SRAM cells, performance metrics and the comparison over different technologies.

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Section: Finfet Technologymentioning

confidence: 99%

A Review On Sram Memory Design Using Finfet Technology

Lakshmi¹,

Kamaraju²

2022

Preprint

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“…MOS channels are formed at the two sidewalls plus top side of the fin. This fin-like geometry, where the depletion regions reach from the gates entirely into the body region, implies that no free charge carriers are available, making the suppression of SCE possible in FinFETs [19][20][21]. Where W is the width of the FinFET device, µ 𝒆𝒇𝒇 is the mobility of electron or holes, 𝐿 𝑒𝑓𝑓 is the channel length of the device, Vt is the constant [ 𝐾𝑇 𝑞 = 26𝑚𝑉]called thermal voltage, Cd is a depletion capacitance, where Vth is a threshold voltage of the transistor, Vgs represent the gate to source voltage of the transistor, Vds is the drain to source voltage, m is the subthreshold slop of the transistor.…”

Section: Finfetmentioning

confidence: 99%

Predictive Evaluation of Currents For Nano Multi FinFETs Under Geometry Variations

Khan¹,

Khan²,

Ajay³

2022

Preprint

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Scaling of the transistor is a prime thrust for development of semiconductor industries. In this paper we have evaluated the impact of ION and IOFF current by applying process variation on different device parameters from 20-7nm of FinFET technology and study the behaviour of the digital circuit with scaling of technology. Here the impact on ION and IOFF current is investigated with the variation of Fins in FinFET transistors for High Performance (HP) and Lower Standby Power (LSTP) models along with applying 10% deviation from nominal values in different device parameters. The simulation results shows that by applying 10% deviation from nominal values of the geometric parameters Length (L) Width (WFin), Hight (HFin), Work Function (WFF), Thickness (TFin), and Source and Drain doping, affects ION current in HP N-FinFET of 20nm technology and has lowest Normalize Standard Deviation of 7% and LSTP P-FinFET in 7nm technology has highest 27% of Normalize Standard deviation. Results also shows that with 3% Normalized Standard Deviation in both HP (N,P FinFET) and LSTP (N,P FinFET) in WFF has an enormous impact on IOFF current i.e. Normalize Standard Deviation of 117% compared to variation in other device parameters which causes maximum Normalize Standard Deviation of 51% and minimum of 5%. Here variations in parameters are done taking 2,4,8,16 fins in FinFET. These experiments are carried on HSPICE simulator at 27°C temperature by using 20-7nm Berkley Predictive Technology Module.

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“…Drain gating technique reduces leakage currents by adding PMOS and NMOS sleep transistors between pull up and pull down network as shown in Figure . During standby mode, both DGP1 and DGN1 sleep transistors are turned off (by giving external signals to S and

\overset{S}{true}

) producing stacking effect making reduction of leakage currents by increasing the resistance of the circuit from V DD to Gnd …”

Section: Literature Reviewmentioning

confidence: 99%

“…During standby mode, both DGP1 and DGN1 sleep transistors are turned off (by giving external signals to S and S) producing stacking effect making reduction of leakage currents by increasing the resistance of the circuit from V DD to Gnd. [23][24][25][26][27]…”

Section: Drain Gating Techniquementioning

confidence: 99%

Integrating flipped drain and power gating techniques for efficient FinFET logic circuits

Dadoria

Khare

Gupta

et al. 2018

Int J Numerical Modelling

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Power dissipation is a main attention for designing complementary metal oxide semiconductor Very Large Scale Integration (VLSI) circuits in deep sub‐micron technology. Constant field device scaling leads to high transistor density, reduction in power supply, lower threshold voltage, and reduction in oxide thickness. This gives rise to short channel effects and increases the leakage currents causing power dissipation. In this paper, based on literature survey, new flipped drain gating (FDG) technique is proposed for mitigation of leakage currents; further FDG technique is integrated with power gating technique which makes power dissipation lower than FDG. Proposed techniques are integrated with FinFET technology and applied on Logic Gates and bench mark circuits on HSPICE simulator. Simulation is carried out at 27°C temperature by using 20 to 7‐nm Berkley Predictive Technology Module. Simulation results at 10‐MHz frequency shows maximum saving in leakage power using FDG technique at input vector 01 as 80.35% compared with conventional drain gating for EXOR logic. Similarly, FDG technique saves maximum dynamic power of 25.98% when compared with conventional drain gating for AND logic.

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Leakage Reduction by Using FinFET Technique for Nanoscale Technology Circuits

Cited by 8 publications

References 0 publications

A Review On Sram Memory Design Using Finfet Technology

A Review On Sram Memory Design Using Finfet Technology

Predictive Evaluation of Currents For Nano Multi FinFETs Under Geometry Variations

Integrating flipped drain and power gating techniques for efficient FinFET logic circuits

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