LEAKAGE POWER REDUCTION THROUGH DUAL V_th ASSIGNMENT CONSIDERING THRESHOLD VOLTAGE VARIATION

Abstract

†In today's sub-100nm CMOS technologies, leakage current has become an important part of the total power consumption, affecting both yields and lifetime of digital circuits. Dual V th assignment, which is proven to be an effective method of reducing leakage power in the past, is also effective in today's technologies with certain modifications. In the paper, based on a statistical timing analysis (SSTA) framework we presented a dual V th assignment method which can effectively reduce the leakage power even in the presence of large V th variation. Besides, we use a statistical DAG pruning method which takes correlation between gates into account to speed up the dual V th assignment algorithm. Experimental results show that statistical dual V th assignment can reduce on average 40% more leakage current compared with conventional static method without affecting the performance constraints. Our DAG pruning method can reduce on average 30% gates in the circuit and save up to 50% of the total run time.