Leakage power modeling and optimization in interconnection networks

Abstract

Power will be the key limiter to system scalability as interconnection networks take up an increasingly significant portion of system power. In this paper, we propose an architectural leakage power modeling methodology that achieves 95-98% accuracy against HSPICE estimates. When applied to interconnection networks, combined with previous proposed dynamic power models, we gain valuable insights on total network power consumption. Our modeling shows router buffers to be a prime candidate for leakage power optimization. We thus investigate the design space of power-aware buffer policies, propose a suite of policies, and explore the impact of various circuits mechanisms on these policies. Simulations show power-aware buffers saving up to 96.6% of total buffer leakage power.

FlexiBuffer

“…However, the actual buffers that are not utilized vary with different traffic patterns and network load; thus, removing unutilized buffers is not a practical option while reducing the overall buffer space can cause performance degradation, 1 Other traffic pattern causes a more imbalance in buffer utilization while uniform random traffic creates the most random (or loadbalanced) traffic. 2 For the routers on the edge of the 2D mesh network, some of the ports are not connected and we ignore the impact of those buffers in this work and assume they are always power-gated. as shown earlier in Figure 1.…”

“…The techniques described in this work can be extended to intermediate buffers to minimize their leakage power. Power-aware buffers [2] were proposed to minimize leakage power, and they described different design spaces of power-aware buffers. Our microarchitecture can be classified as predictive according to their terminology [2].…”

“…Power-aware buffers [2] were proposed to minimize leakage power, and they described different design spaces of power-aware buffers. Our microarchitecture can be classified as predictive according to their terminology [2]. However, they do not provide details of implementing different power-aware buffers, and their study focused on large-scale, off-chip networks, whereas our work focuses on on-chip networks which have different constraints [3].…”

Design of application-specific 3D Networks-on-Chip architectures

“…The ports of routers on the same layer are connected by horizontal interconnects whereas the ports of routers on different layers are connected by 3D interconnects. We use a state-of-the-art NoC power-performance simulator called Orion [32], [33] that can provide detailed power characteristics for different power components of a router for different input/output port configurations. It accurately considers leakage power as well as dynamic switching power.…”

“…As discussed in Section V, we use Orion [32], [33] to estimate the power consumptions of router configurations generated. We applied the design parameters of 1 GHz clock frequency, 4-flit buffers, and 128-bit flits.…”