Leakage energy management in cache hierarchies

Li, L.; Kadayif, I.; Tsai, Yuh-Fang; Narayanan, Vijaykrishnan; Kandemir, Mahmut; Irwin, M.; Sivasubramaniam, Anand

doi:10.1109/pact.2002.1106012

Cited by 68 publications

(56 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Other state-preserving techniques have been proposed in [9], [12]. This may be achieved by lowering the V dd .…”

Section: Related Workmentioning

confidence: 99%

“…Since precise and stable threshold voltage is difficult to achieve in deep submicron processes, this makes the cells more susceptible to soft errors and metastability. Furthermore, in [9], several architectural techniques that exploit the data duplication across the different levels of cache hierarchy are proposed and compared to multi-level decay techniques both exploiting state-preserving and statedestroying mechanisms. For the reasons above, this work focuses only on state-destroying techniques (i.e.…”

Section: Related Workmentioning

confidence: 99%

“…Otherwise, when the line is accessed, the counter is reset to its initial value (decay time). Cache decay has been mostly studied in the context of L1 caches and only recently has been considered also for L2 caches [9], [10].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs

Monchiero

Canal

González

2009

2009 International Conference on Parallel Processing

View full text Add to dashboard Cite

Abstract-This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching off the less used lines. We primarily focus on private snoopy L2 caches. In this case, coherence must be enforced in all situations and specially when a line is turned off to save power. In particular, we introduce three techniques: the first one turns off the cache lines by using the coherence protocol invalidations, the second one is an implementation of a cache decay technique specific for coherent caches, the third one is a performance-optimized decay-based technique for coherent caches.Experimental results, carried out by using accurate performance/thermal/energy models, show that appreciable power savings can be achieved by properly designing a leakage optimization technique. We target a CMP composed of 4 cores and 1 to 8 MB of total cache. For 4MB, the proposed techniques show a 13%, 30%, and 21% energy reduction, respectively, at the cost of 0%, 8%, and 2% performance loss. For other cache sizes the behavior is qualitatively similar.

show abstract

“…Other state-preserving techniques have been proposed in [9], [12]. This may be achieved by lowering the V dd .…”

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs

Monchiero

Canal

González

2009

2009 International Conference on Parallel Processing

View full text Add to dashboard Cite

show abstract

“…Li et. al [27] presented in 2002 several architectural techniques that exploit the data duplication across the different levels of cache hierarchy. Multiple states with progressive reduction of voltage supply before the data loosing are proposed by Mohyuddin et al [20].…”

Section: Related Workmentioning

confidence: 99%

Reducing Leakage through Filter Cache

Giorgi

Bennati

2008

2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools

View full text Add to dashboard Cite

show abstract

“…However the costs of larger caches are significant and growing. They typically occupy 40-60% of the chip area [14] and with leakage power exceeding switching power at sub-micron technologies [11,10], they are dominant consumers of energy. Furthermore, analysis of benchmarks have shown that cache utilization is typically low -below 20% for a majority of benchmarks [8,4] with performance efficiency averaging 4.7% and energy efficiency averaging 0.17%!…”

Section: Introductionmentioning

confidence: 99%

Improving cache efficiency via resizing + remapping

Ramaswamy

Yalamanchili

2007

2007 25th International Conference on Computer Design

View full text Add to dashboard Cite

In this paper we propose techniques to dynamically downsize or upsize a cache accompanied by cache set/line shutdown to produce efficient caches. Unlike previous approaches, resizing is accompanied by a non-uniform remapping of memory into the resized cache, thus avoiding misses to sets/lines that are shut off. The paper first provides an analysis into the causes of energy inefficiencies revealing a simple model for improving efficiency. Based on this model we propose the concept of "folding" -memory regions mapping to disjoint cache resources are combined to share cache sets producing a new placement function. Folding enables powering down cache sets at the expense of possibly increasing conflict misses. Effective folding heuristics can substantially increase energy efficiency at the expense of acceptable increase in execution time. We target the L2 cache because of its larger size and greater energy consumption. Our techniques increase cache energy efficiency by 20%, and reduce the EDP (energy delay product) by up to 45% with an IPC degradation of less than 4%. The results also indicate opportunity for improving cache efficiencies further via cooperative compiler interactions.

show abstract

Leakage energy management in cache hierarchies

Cited by 68 publications

References 9 publications

Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs

Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs

Reducing Leakage through Filter Cache

Improving cache efficiency via resizing + remapping

Contact Info

Product

Resources

About