Leakage current model of InGaZnO thin film transistor

Deng, X.Q.; Deng, Lian-Wen; He, Yi-Ni; Liao, Congwei; Huang, Shengxiang; Luo, Hui

doi:10.7498/aps.68.20182088

Acta Phys. Sin.

2019

DOI: 10.7498/aps.68.20182088

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Leakage current model of InGaZnO thin film transistor

X.Q. Deng¹,

Lian-Wen Deng²,

Yi-Ni He³

et al.

Abstract: <sec>In recent years, amorphous InGaZnO thin-film transistor (InGaZnO TFT) has attracted intensive attention. Due to its high mobility, low off-state current, and excellent uniformity over large fabrication area, the InGaZnO TFTs promise to replace silicon-based TFTs in flat panel displays, optical image sensors, touch sensing and fingerprint sensing area. The on-state performances of InGaZnO TFT are used in thin film transistor liquid crystal display, active-matrix organic light emitting display, etc. C… Show more

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Cited by 2 publications

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Electro-static discharge failure analysis and design optimization of gate-driver on array circuit in InGaZnO thin film transistor backplane

Ma¹,

Zhou²,

Yu³

et al. 2019

Acta Phys. Sin.

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There is a risk of InGaZnO thin film transistor (IGZO TFT) failure, especially electro-static discharge (ESD) damage of gate driver on array (GOA) circuits, due to the combination of Cu interconnect, InGaZnO (IGZO) active layer and SiNx/SiO2 insulating layer used to realize large-scale ultra-high resolution display. It is found that the IGZO TFT damage position caused by ESD occurs between the source/drain metal layer and the gate insulator. The Cu metal of gate electrode diffuses into the gate insulator of SiNx/SiO2. The closer to the ESD damage area the IGZO TFT is, the more serious the negative bias of its threshold voltage (Vth) is until the device is fully turned on. The IGZO TFT with a large channel width-to-length ratio(W/L) in GOA circuit results in a serious negative bias of threshold voltage. In this paper, the ESD failure problem of GOA circuit in the IGZO TFT backplane is systematically analyzed by combining the ESD device level analysis with the system level analysis, which combines IGZO TFT device technology, difference in metal density between GOA region and active area on backplane, non-uniform thickness distribution of gate metal layer and gate insulator and so on. In the analysis of ESD device level, we propose that the diffusion of Cu metal from gate electrode into SiNx/SiO2 leads to the decrease of effective gate insulator layer, and that the built-in space charge effect leads to the decrease of the anti-ESD damage ability of IGZO TFT. In the analysis of ESD system level, we propose that the density of metal layers in GOA region is 4.5 times higher than that in active area of display panel, which makes the flatness of metal layer in GOA region worse. The non-uniformity of thickness of Cu metal film, SiNx film and SiO2 film around glass substrate lead to the position dependence of the anti-ESD damage ability of IGZO TFT in the GOA region. If there is a transition zone of film thickness change in IGZO TFT with large area, the ESD failure will occur easily. Accordingly, we propose to split large area IGZO TFT into several sub-TFT structures, which can effectively improve the ESD failure.

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Electro-static discharge failure analysis and design optimization of gate-driver on array circuit in InGaZnO thin film transistor backplane

Ma¹,

Zhou²,

Yu³

et al. 2019

Acta Phys. Sin.

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Electro-static discharge protection analysis and design optimization of interlayer Cu interconnection in InGaZnO thin film transistor backplane

Ma¹,

Wang²,

Zhang³

et al. 2019

Acta Phys. Sin.

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The InGaZnO thin film transistor (IGZO TFT) backplane combined with Cu interconnection has nearly an order of magnitude lower in the ability to withstand voltage than that of traditional a-Si TFT backplane on the production line. The breakdown voltage of Mo/Cu interconnection between data line and gate line is only about 60% of that of traditional a-Si TFT backplane. The electrostatic discharge (ESD) breakdown of Mo/Cu:SiNx/SiO2:Mo/Cu structure has become an important factor affecting the normal display of IGZO TFT ultra high definition (UHD) panel. We find that the anti-ESD damage ability of IGZO TFT devices needs matching with the anti-ESD damage ability of interlayer Cu interconnection in order to achieve a high-robustness IGZO TFT backplane. The position of ESD damage in IGZO TFT backplane is commonly in the climbing place where the data line crosses the scanning line. In this paper, a Cu diffusion model is proposed to explain the mechanism for the ESD failure of interlayer Cu interconnection. The Cu metal in gate line diffuses into SiNx/SiO2 gate insulator, and Cu metal at the corner of data line, where the date line crosses the gate line, diffuses into SiO2 film on the date line. The selection conditions of three kinds of protection architectures for ESD protection circuits around Cu interconnection, i.e. R-type, R-half-type, and Diode-type protection architectures, are proposed. On the basis of process optimization such as Cu metal film forming and Cu metal interface treatment, an ESD protection method for the Cu interconnection periphery of IGZO TFT backplane with high robustness is proposed. For the stable production process of IGZO TFT, combined with the design window of ESD protection circuit, the peripheral ESD protection circuit of Cu interconnect is designed with diode-type protection circuit on the IGZO TFT backplane of large-sized UHD and QUHD panel, which effectively improves the effect of interlayer Cu interconnection of IGZO TFT backplane on ESD damage. Through the production verification, it is proved that the metal diffusion of Cu interconnection on IGZO TFT backplane is the fundamental reason for reducing the anti-ESD damage ability of Mo/Cu:SiNx/SiO2:Mo/Cu structure. The rationality of the proposed ESD damage model for interlayer Cu interconnection is verified, which provides a theoretical basis for subsequent IGZO TFT backplane design with high robustness.

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Leakage current model of InGaZnO thin film transistor

Cited by 2 publications

References 27 publications

Electro-static discharge failure analysis and design optimization of gate-driver on array circuit in InGaZnO thin film transistor backplane

Electro-static discharge failure analysis and design optimization of gate-driver on array circuit in InGaZnO thin film transistor backplane

Electro-static discharge protection analysis and design optimization of interlayer Cu interconnection in InGaZnO thin film transistor backplane

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