Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs

Abstract

3D IC has become an attractive technology as it decreases interconnection distance and improves performance. However, it is faced with heat dissipation and temperature problem seriously. The high temperature will increase the interconnection delay, and lead to degradation of performance. Through-silicon-via (TSV) has been shown as an effective way to optimize heat distribution. However, the distribution of TSVs will potentially influence the interconnection delay. In this paper, we propose a performance-driven 3D TSV-planning (3D-PTSP) algorithm, which can generate good TSV distribution, to improve temperature. The thermal effects on critical path delay are analyzed with leakage power-temperature-delay dependence considered. A priority based TSV redistribution algorithm and network flow based signal via allocation algorithm help to improve both TSV number and critical path delay without increasing temperature. Experimental results show that the proposed method can improve total via number by 8.9% and reduce critical path delay by 15.8%.