LEAD: An Adaptive 3D-NoC Routing Algorithm with Queuing-theory Based Analytical Verification

Abstract

2D-NoCs have been the mainstream approach used to interconnect multi-core systems. 3D-NoCs have emerged to compensate for deficiencies of 2D-NoCs such as long latency and power overhead. A low-latency routing algorithm for 3D-NoC is designed to accommodate high-speed communication between cores. Both simulation and analytical models are applied to estimate the communication latency of NoCs. Generally, simulations are time-consuming and slow down the design process. Analytical models provide, within a fraction of the time, nearly accurate results which can be used by simulation to fine-tune the design. In this paper, a high performance and adaptive routing algorithm has been proposed for partially connected 3D-NoCs. Latency of the routing algorithm under different traffic patterns, different number of elevators and different elevator assignment mechanisms are reported. An analytical model, tailored to the adaptivity of the algorithm and under low traffic scenarios, has been developed and the results have been verified by simulation. According to the results, simulation and analytical results are consistent within a 10 percent margin.

AdEle: An Adaptive Congestion-and-Energy-Aware Elevator Selection for Partially Connected 3D NoCs

“…Moreover, as the elevatorless routers cannot directly send packets to other layers, an elevator is selected for each packet to facilitate the inter-layer communication. Leveraging such a principle, several routing algorithms have been proposed for PC-3DNoCs [3], [14]. However, they follow an elevator-selection policy that ignores elevators' load distribution and the minimal path.…”

Deadlock‐free adaptive 3D network‐on‐chips routing algorithm with repetitive turn concept

“…LEAD [37] takes into account the vertical partial connectivity in 3D NoCs. The number of VCs of this algorithm is the same as elevator-first along different dimensions, and divides the network into five disjoint subnetworks virtually.…”

Interval Based Transaction Record Keeping Mechanism for Adaptive 3D Network-on-Chip Routing

“…NoC also enhances performance in the form of throughput, latency and scalability compared to traditional interconnection architectures. However, thermal aggravation [2], transient and permanent defects [3], aging [4], high power density [5], and congestion [6] are some of the variables that contribute to NoC performance deterioration.…”